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Course Description

Course Map

Interactive map showing all 13 units and their prerequisite relationships. Click a unit to see its connections, drag nodes to rearrange.

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Course Information

  • Course Title: Introduction to Digital System Design
  • Course Code: EE 2301
  • Institution: University of Minnesota – Twin Cities
  • Department: Electrical & Computer Engineering
  • Credits: 3

Target Audience

This course is designed for:

  • Sophomore and junior-level Electrical Engineering students
  • Computer Engineering students
  • Students pursuing minors in electronics or embedded systems
  • Anyone seeking foundational knowledge in digital logic design

Prerequisites

Students should have completed or have equivalent knowledge in:

  • Basic algebra and mathematical reasoning
  • Introduction to programming (any language)
  • Familiarity with basic circuit concepts (recommended but not required)

Course Description

This course provides a comprehensive introduction to the fundamentals of digital system design. Students will learn how digital circuits process information using binary number systems and Boolean algebra. The course covers the mathematical foundations, analysis techniques, and design methodologies essential for creating both combinational and sequential digital logic circuits.

Topics progress from number representations through Boolean algebra to systematic methods for designing and simplifying logic circuits. Students will gain hands-on experience with truth tables, logic gates, Karnaugh maps, the Quine-McCluskey method, multi-level gate implementations, combinational modules, and sequential circuit design including latches, flip-flops, registers, counters, and finite state machines. The course culminates with programmable logic devices, introduction to VHDL hardware description language, and system integration projects that bring together all concepts into complete digital system designs.

Topics Covered

Unit 1: Number Systems

  • Decimal, binary, octal, and hexadecimal number systems
  • Positional notation and base conversions
  • Binary arithmetic operations
  • Signed number representations (signed magnitude, 1's complement, 2's complement)
  • Overflow detection in arithmetic operations

Unit 2: Boolean Algebra

  • Boolean variables and constants
  • Basic logic operators (AND, OR, NOT)
  • Derived operators (NAND, NOR, XOR, XNOR)
  • Boolean identities and theorems
  • DeMorgan's theorems
  • Algebraic simplification techniques

Unit 3: Applications of Boolean Algebra

  • Converting English statements to Boolean equations
  • Combinational logic design using truth tables
  • Design of binary adders and subtractors (Half Adder, Full Adder)
  • Incompletely specified functions

Unit 4: Minterm and Maxterm Expansions

  • Canonical Sum of Products (SOP) form
  • Canonical Product of Sums (POS) form
  • Conversion between minterm and maxterm forms
  • Don't care conditions in logic design

Unit 5: Karnaugh Maps

  • 2-variable, 3-variable, 4-variable, and 5-variable K-maps
  • Grouping rules and simplification techniques
  • Prime implicants and essential prime implicants
  • K-map simplification for SOP and POS forms
  • K-maps with don't care conditions

Unit 6: Quine-McCluskey Method

  • Systematic tabular minimization algorithm
  • Implicant table construction and minterm combination
  • Prime implicant generation and charts
  • Essential prime implicant identification
  • Minimum cover determination and Petrick's method

Unit 7: Multi-Level Gate Circuits

  • Two-level vs multi-level circuit implementations
  • Universal gates (NAND and NOR) and their properties
  • AND-OR to NAND-NAND conversion
  • OR-AND to NOR-NOR conversion
  • Bubble pushing technique
  • Propagation delay and critical path analysis

Unit 8: Combinational Logic Modules

  • Multiplexers (MUX) and demultiplexers (DEMUX)
  • Encoders and priority encoders
  • Decoders and their applications
  • Function implementation using MUX and decoders
  • Memory addressing and data bus management

Unit 9: Sequential Logic Fundamentals

  • Combinational vs sequential circuits
  • Basic memory elements: SR, D, JK, and T latches
  • Edge-triggered flip-flops
  • Clock signals and synchronous design
  • Setup time, hold time, and timing constraints
  • Timing diagram interpretation

Unit 10: Sequential Circuit Design

  • Registers: parallel load and shift registers
  • Counters: binary, BCD, up/down, and ring counters
  • Finite state machine (FSM) concepts
  • Mealy and Moore machine models
  • State diagram and state table development
  • FSM design methodology and implementation

Unit 11: Programmable Logic Devices

  • Fixed logic vs programmable logic
  • ROM as a logic device (PROM, EPROM, EEPROM, Flash)
  • Programmable Logic Array (PLA) architecture
  • Programmable Array Logic (PAL) architecture
  • PLA vs PAL trade-offs
  • Complex PLD (CPLD) architecture and macrocells
  • Field-Programmable Gate Array (FPGA) concepts
  • Lookup tables (LUTs) and configurable logic blocks (CLBs)
  • FPGA design flow and technology mapping

Unit 12: Introduction to VHDL

  • Entity declarations and architecture bodies
  • Ports, port modes, and VHDL data types (std_logic, std_logic_vector)
  • Signal declaration and assignment
  • Concurrent, conditional, and selected signal assignment
  • Structural, behavioral, and dataflow modeling
  • Process statements and sensitivity lists
  • Combinational and sequential logic in VHDL
  • D flip-flops, registers, counters, and FSMs in VHDL
  • Testbench fundamentals and simulation

Unit 13: System Integration and Design Projects

  • Top-down design methodology and system partitioning
  • Datapath and control unit separation
  • Datapath-controller integration
  • Verification planning and testbench architecture
  • Static timing analysis and critical path identification
  • Setup and hold time budgeting
  • Design trade-offs: area vs speed vs power
  • System-level design examples (digital lock, ALU, vending machine controller)
  • From specification to silicon

Learning Outcomes

Upon successful completion of this course, students will be able to:

Remember

  • Define the four primary number systems used in digital design (decimal, binary, octal, hexadecimal)
  • List the basic Boolean operators and their symbols
  • Identify the components of a Karnaugh map
  • Recall the characteristics of common flip-flop types (SR, D, JK, T)
  • Name the major programmable logic device families (ROM, PLA, PAL, CPLD, FPGA)
  • List the basic VHDL design units (entity, architecture)

Understand

  • Explain how positional notation represents numerical values in different bases
  • Describe the relationship between Boolean algebra and digital logic gates
  • Summarize DeMorgan's theorems and their applications
  • Explain the difference between combinational and sequential circuits
  • Describe the operation of multiplexers, decoders, and encoders
  • Explain the differences between PLA, PAL, CPLD, and FPGA architectures
  • Describe how lookup tables (LUTs) implement Boolean functions in FPGAs
  • Explain the distinction between concurrent and sequential statements in VHDL
  • Describe the top-down design methodology for digital systems

Apply

  • Convert numbers between decimal, binary, octal, and hexadecimal systems
  • Perform binary arithmetic including addition and subtraction using 2's complement
  • Use Boolean algebra to simplify logic expressions
  • Construct truth tables for combinational logic circuits
  • Apply the Quine-McCluskey method to minimize Boolean functions
  • Convert circuits to NAND-only or NOR-only implementations
  • Interpret timing diagrams for sequential circuits
  • Write VHDL entity declarations and architecture bodies for combinational circuits
  • Implement flip-flops, registers, and counters in VHDL
  • Write VHDL testbenches for simulation and verification

Analyze

  • Differentiate between SOP and POS canonical forms
  • Compare signed number representation methods and their trade-offs
  • Examine logic circuits to identify optimization opportunities
  • Analyze timing constraints including setup and hold times
  • Distinguish between Mealy and Moore state machine models
  • Compare programmable logic device families and their trade-offs
  • Analyze critical paths and determine maximum clock frequency
  • Partition digital systems into datapath and control unit components

Evaluate

  • Assess the efficiency of different logic simplification methods
  • Critique circuit designs for minimality and correctness
  • Judge when to use K-maps versus Quine-McCluskey method
  • Evaluate trade-offs between gate count and propagation delay
  • Select appropriate programmable logic devices for given design requirements
  • Evaluate design trade-offs between area, speed, and power

Create

  • Design combinational logic circuits from problem specifications
  • Construct K-maps and derive minimal Boolean expressions
  • Develop digital circuits for arithmetic operations (adders, subtractors)
  • Design registers and counters for specific applications
  • Create finite state machines from behavioral specifications
  • Describe complete digital systems in VHDL
  • Design and implement integrated digital systems (digital lock, ALU, vending machine controller)
  • Develop verification plans and testbenches for digital designs

Assessment Methods

  • Weekly problem sets with worked examples
  • Interactive quizzes aligned with Bloom's Taxonomy levels
  • MicroSim-based practice with immediate feedback
  • Unit examinations
  • Design projects

Required Materials

  • This intelligent textbook (online, free access)
  • Scientific calculator capable of base conversions (recommended)
  • Access to logic simulation software (optional, for advanced practice)

Course Format

This intelligent textbook provides:

  • Clear, student-friendly explanations of all concepts
  • Step-by-step worked examples with detailed solutions
  • Interactive MicroSims for visualizing logic operations
  • Auto-generated practice problems with instant feedback
  • Visual learning aids including truth tables, logic diagrams, and K-maps