{ "metadata": { "title": "Introduction to Digital System Design", "description": "A comprehensive learning graph covering digital system fundamentals including number systems, Boolean algebra, logic gates, combinational circuits, canonical forms, and Karnaugh map simplification techniques for EE 2301.", "creator": "University of Minnesota - Twin Cities", "date": "2026-02-04", "version": "1.0", "format": "Learning Graph JSON v1.0", "schema": "https://raw.githubusercontent.com/dmccreary/learning-graphs/refs/heads/main/src/schema/learning-graph-schema.json", "license": "CC BY-NC-SA 4.0 DEED" }, "groups": { "FOUND": { "classifierName": "Foundation Concepts", "color": "LightCoral", "font": { "color": "white" } }, "NUMSYS": { "classifierName": "Number Systems", "color": "PeachPuff", "font": { "color": "black" } }, "CONV": { "classifierName": "Number Conversions", "color": "LightYellow", "font": { "color": "black" } }, "ARITH": { "classifierName": "Binary Arithmetic", "color": "PaleGreen", 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"chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [], "dependents": [ 2, 3, 44 ], "microsims": [ "course-structure-tree" ] }, "2": { "id": 2, "label": "Analog vs Digital Signals", "group": "FOUND", "category": "Foundation Concepts", "definition": "The distinction between continuously varying analog signals and digital signals restricted to a finite set of discrete voltage levels.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": 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"unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 7, 8 ], "dependents": [], "microsims": [] }, "10": { "id": 10, "label": "Bit", "group": "FOUND", "category": "Foundation Concepts", "definition": "The fundamental unit of digital information, representing a single 0 or 1; the term is a portmanteau of \"binary\" and \"digit.\"", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 3 ], "dependents": [ 11, 14, 15, 26, 27, 30, 31 ], "microsims": [] }, "11": { "id": 11, "label": "Nibble", "group": "FOUND", "category": "Foundation Concepts", "definition": "A unit of digital data consisting of 4 bits that can represent 16 distinct values (0\u201315 in decimal, or 0\u2013F in hexadecimal); each hexadecimal digit corresponds to exactly one nibble.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 10 ], "dependents": [ 12, 24, 25 ], "microsims": [] }, "12": { "id": 12, "label": "Byte", "group": "FOUND", "category": "Foundation Concepts", "definition": "A unit of digital data comprising 8 bits (2 nibbles) that can represent 256 distinct values (0\u2013255 unsigned) and serves as the standard addressable unit of memory in most computer architectures.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 11 ], "dependents": [ 13, 35 ], "microsims": [] }, "13": { "id": 13, "label": "Word", "group": "FOUND", "category": "Foundation Concepts", "definition": "A processor-specific unit of data representing the natural data size for a particular architecture (e.g., 32 bits or 64 bits), affecting memory addressing, register width, and arithmetic precision.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 12 ], "dependents": [], "microsims": [] }, "14": { "id": 14, "label": "Most Significant Bit", "group": "FOUND", "category": "Foundation Concepts", "definition": "The leftmost bit in a binary number, which contributes the largest positional value; in signed number representations, the MSB typically indicates the sign of the number.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 3, 10 ], "dependents": [ 32, 35, 132, 133 ], "microsims": [] }, "15": { "id": 15, "label": "Least Significant Bit", "group": "FOUND", "category": "Foundation Concepts", "definition": "The rightmost bit in a binary number, which contributes the smallest positional value (either 0 or 1) to the overall number.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 3, 10 ], "dependents": [ 132, 133 ], "microsims": [] }, "16": { "id": 16, "label": "Binary to Decimal Conversion", "group": "CONV", "category": "Number Conversions", "definition": "The process of finding the decimal value of a binary number by summing the weights of each bit position that contains a 1.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", 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"id": 18, "label": "Octal to Decimal Conversion", "group": "CONV", "category": "Number Conversions", "definition": "The process of finding the decimal value of an octal number by summing each digit multiplied by its positional power of 8.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 4, 5, 7 ], "dependents": [], "microsims": [ "base-converter" ] }, "19": { "id": 19, "label": "Decimal to Octal Conversion", "group": "CONV", "category": "Number Conversions", "definition": "The process of expressing a decimal number in base 8, typically found by repeated division by 8 and recording the remainders.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 4, 5, 7 ], "dependents": [], "microsims": [ "base-converter" ] }, "20": { "id": 20, "label": "Hexadecimal to Decimal", "group": "CONV", "category": "Number Conversions", "definition": "The process of finding the decimal value of a hexadecimal number by summing each digit multiplied by its positional power of 16.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 4, 6, 7 ], "dependents": [], "microsims": [ "base-converter" ] }, "21": { "id": 21, "label": "Decimal to Hexadecimal", "group": "CONV", "category": "Number Conversions", "definition": "The process of expressing a decimal number in base 16, typically found by repeated division by 16 and recording the remainders.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 4, 6, 7 ], "dependents": [], "microsims": [ "base-converter" ] }, "22": { "id": 22, "label": "Binary to Octal Conversion", "group": "CONV", "category": "Number Conversions", "definition": "The process of converting a binary number to octal by grouping bits in sets of three from the radix point and converting each group to its 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bits represent the magnitude, mirroring how humans write signed numbers but having two representations of zero.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 14, 30 ], "dependents": [ 40 ], "microsims": [ "signed-number-comparison" ] }, "33": { "id": 33, "label": "Ones Complement", "group": "ARITH", "category": "Binary Arithmetic", "definition": "A signed number representation in which negative values are formed by inverting every bit of the positive magnitude.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": 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}, "35": { "id": 35, "label": "Sign Extension", "group": "ARITH", "category": "Binary Arithmetic", "definition": "The technique of preserving the numerical value of a signed binary number when increasing its bit width by replicating the sign bit (0s for positive, 1s for negative) into the additional higher-order positions.", "chapter": 1, "chapterTitle": "Number Systems", "chapterDir": "unit1-number-systems", "chapterUrl": "../../unit1-number-systems/", "glossaryUrl": "../../unit1-number-systems/glossary/", "quizUrl": "../../unit1-number-systems/quiz/", "problemsUrl": "../../unit1-number-systems/problems/", "challengeUrl": "../../unit1-number-systems/challenge/", "prerequisites": [ 12, 14, 30 ], "dependents": [ 37 ], "microsims": [] }, "36": { "id": 36, "label": "Twos Complement Addition", "group": "ARITH", "category": "Binary Arithmetic", "definition": "Adding two's complement numbers using ordinary binary addition, where the sign is handled automatically and any carry out of the most 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"../../unit2-boolean-algebra/glossary/", "quizUrl": "../../unit2-boolean-algebra/quiz/", "problemsUrl": "../../unit2-boolean-algebra/problems/", "challengeUrl": "../../unit2-boolean-algebra/challenge/", "prerequisites": [ 41, 47, 48 ], "dependents": [ 80 ], "microsims": [ "boolean-laws-explorer" ] }, "70": { "id": 70, "label": "Involution Law", "group": "THEOR", "category": "Boolean Theorems", "definition": "A Boolean identity stating that complementing a variable twice returns the original value: \\(\\overline{\\overline{A}} = A\\), also known as the double complement law.", "chapter": 2, "chapterTitle": "Boolean Algebra", "chapterDir": "unit2-boolean-algebra", "chapterUrl": "../../unit2-boolean-algebra/", "glossaryUrl": "../../unit2-boolean-algebra/glossary/", "quizUrl": "../../unit2-boolean-algebra/quiz/", "problemsUrl": "../../unit2-boolean-algebra/problems/", "challengeUrl": "../../unit2-boolean-algebra/challenge/", "prerequisites": [ 41, 49, 50 ], "dependents": [ 80 ], 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}, "75": { "id": 75, "label": "Absorption Law", "group": "THEOR", "category": "Boolean Theorems", "definition": "A Boolean theorem that eliminates redundant terms from an expression, stated as \\(A + AB = A\\) and \\(A(A + B) = A\\).", "chapter": 2, "chapterTitle": "Boolean Algebra", "chapterDir": "unit2-boolean-algebra", "chapterUrl": "../../unit2-boolean-algebra/", "glossaryUrl": "../../unit2-boolean-algebra/glossary/", "quizUrl": "../../unit2-boolean-algebra/quiz/", "problemsUrl": "../../unit2-boolean-algebra/problems/", "challengeUrl": "../../unit2-boolean-algebra/challenge/", "prerequisites": [ 41, 74 ], "dependents": [ 76, 80 ], "microsims": [ "boolean-laws-explorer" ] }, "76": { "id": 76, "label": "Consensus Theorem", "group": "THEOR", "category": "Boolean Theorems", "definition": "A Boolean theorem that identifies and eliminates a redundant consensus term, stated as \\(AB + \\overline{A}C + BC = AB + \\overline{A}C\\), where the \\(BC\\) term is already covered by the other two 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"../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 26, 102 ], "dependents": [ 103 ], "microsims": [] }, "105": { "id": 105, "label": "Sum Bit", "group": "ACIR", "category": "Arithmetic Circuits", "definition": "The lower-order output of an adder circuit, representing the single-bit arithmetic sum of the input bits at a given position (computed as the XOR of the inputs and any carry-in).", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 58, 102 ], "dependents": [ 103 ], "microsims": [] }, "106": { "id": 106, "label": "Ripple Carry Adder", "group": "ACIR", "category": "Arithmetic Circuits", "definition": "A multi-bit adder constructed by chaining \\(n\\) full adders in series, where the carry-out of each stage connects to the carry-in of the next, causing carries to \"ripple\" sequentially from LSB to MSB.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 89, 103 ], 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"group": "ACIR", "category": "Arithmetic Circuits", "definition": "A combinational circuit that subtracts one bit from another while accounting for a borrow-in from a previous stage, producing a difference bit and a borrow-out bit for cascaded multi-bit subtraction.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 107, 109, 110 ], "dependents": [ 111 ], "microsims": [ "adder-subtractor-builder" ] }, "109": { "id": 109, "label": "Borrow Bit", "group": "ACIR", "category": "Arithmetic Circuits", "definition": "The output of a subtractor circuit that indicates when the minuend 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"unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 58, 107 ], "dependents": [ 108 ], "microsims": [] }, "111": { "id": 111, "label": "Adder Subtractor Circuit", "group": "ACIR", "category": "Arithmetic Circuits", "definition": "A combinational circuit that uses a shared set of full adders with XOR gates and a mode control signal M to perform either binary addition (M=0) or two's complement subtraction (M=1) on multi-bit operands.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": 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"../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 112 ], "dependents": [ 271 ], "microsims": [ "magnitude-comparator" ] }, "114": { "id": 114, "label": "Parity Generator", "group": "ACIR", "category": "Arithmetic Circuits", "definition": "A circuit that computes a parity bit for a given data word by XORing all data bits together, producing the bit needed to establish even or odd parity for error detection during transmission.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 58, 89 ], "dependents": [ 115, 116, 117 ], "microsims": [ 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"chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 55, 114 ], "dependents": [ 115 ], "microsims": [] }, "118": { "id": 118, "label": "Code Converter", "group": "ACIR", "category": "Arithmetic Circuits", "definition": "A combinational circuit that translates data from one binary representation (such as BCD, Gray code, or Excess-3) to another, enabling interoperability between subsystems that use different encoding schemes.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 91, 95 ], "dependents": [ 121, 122, 124 ], "microsims": [ "code-converter-demo" ] }, "119": { "id": 119, "label": "BCD Code", "group": "NUMSYS", "category": "Number Systems", "definition": "Binary-Coded Decimal, a code that represents each decimal digit (0-9) independently using a 4-bit binary pattern.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 3, 4 ], "dependents": [ 121 ], "microsims": [] }, "120": { "id": 120, "label": "Gray Code", "group": "NUMSYS", "category": "Number Systems", "definition": "A binary encoding in which consecutive values differ in exactly one bit position, eliminating ambiguous intermediate readings in applications such as rotary position encoders and providing the ordering used in Karnaugh maps.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 3 ], "dependents": [ 122, 169 ], "microsims": [ "binary-gray-converter" ] }, "121": { "id": 121, "label": "BCD to Binary Converter", "group": "ACIR", "category": "Arithmetic Circuits", "definition": "A code conversion circuit that translates a BCD representation into pure binary by multiplying the tens digit by ten and adding the units digit, requiring multiplier and adder sub-circuits.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 118, 119 ], "dependents": [], "microsims": [ "code-converter-demo" ] }, "122": { "id": 122, "label": "Binary to Gray Converter", "group": "ACIR", "category": "Arithmetic Circuits", "definition": "A circuit that converts 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and selected letters.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 6 ], "dependents": [ 124 ], "microsims": [] }, "124": { "id": 124, "label": "Seven Segment Decoder", "group": "ACIR", "category": "Arithmetic Circuits", "definition": "A combinational circuit that converts a 4-bit BCD input into seven output signals (a through g), each controlling one segment of a seven-segment display to form a visible decimal digit.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 118, 123 ], "dependents": [], "microsims": [ "seven-segment-decoder" ] }, "125": { "id": 125, "label": "Incompletely Specified Func", "group": "CANON", "category": "Canonical Forms", "definition": "A Boolean function whose output is not defined for every possible input combination, leaving some input combinations as don't-care conditions.", "chapter": 3, "chapterTitle": "Applications of Boolean Algebra", "chapterDir": "unit3-applications-boolean-algebra", "chapterUrl": "../../unit3-applications-boolean-algebra/", "glossaryUrl": "../../unit3-applications-boolean-algebra/glossary/", "quizUrl": "../../unit3-applications-boolean-algebra/quiz/", "problemsUrl": "../../unit3-applications-boolean-algebra/problems/", "challengeUrl": "../../unit3-applications-boolean-algebra/challenge/", "prerequisites": [ 64, 66, 148 ], "dependents": [ 149 ], "microsims": [] }, "126": { "id": 126, "label": "Canonical Form", "group": "CANON", "category": "Canonical Forms", "definition": "A standard representation of a Boolean function where each term contains all variables in the function, either in complemented or uncomplemented form.", "chapter": 4, "chapterTitle": "Minterm and Maxterm Expansions", "chapterDir": "unit4-minterm-maxterm-expansions", "chapterUrl": "../../unit4-minterm-maxterm-expansions/", "glossaryUrl": "../../unit4-minterm-maxterm-expansions/glossary/", "quizUrl": "../../unit4-minterm-maxterm-expansions/quiz/", "problemsUrl": "../../unit4-minterm-maxterm-expansions/problems/", "challengeUrl": "../../unit4-minterm-maxterm-expansions/challenge/", "prerequisites": [ 84, 85 ], "dependents": [ 127, 138, 139 ], "microsims": [] }, "127": { "id": 127, "label": "Standard Form", "group": "CANON", "category": "Canonical Forms", "definition": "A Boolean expression written as either sum-of-products or product-of-sums but not necessarily in canonical form.", "chapter": 4, "chapterTitle": "Minterm and Maxterm Expansions", "chapterDir": "unit4-minterm-maxterm-expansions", "chapterUrl": "../../unit4-minterm-maxterm-expansions/", "glossaryUrl": "../../unit4-minterm-maxterm-expansions/glossary/", "quizUrl": "../../unit4-minterm-maxterm-expansions/quiz/", "problemsUrl": "../../unit4-minterm-maxterm-expansions/problems/", "challengeUrl": "../../unit4-minterm-maxterm-expansions/challenge/", "prerequisites": [ 126 ], "dependents": [ 184 ], "microsims": [] }, "128": { "id": 128, "label": "Minterm", "group": "CANON", "category": "Canonical Forms", "definition": "A product term containing all variables of a function, each appearing either complemented or uncomplemented.", "chapter": 4, "chapterTitle": "Minterm and Maxterm Expansions", "chapterDir": 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"chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 56, 61, 84 ], "dependents": [ 231, 232, 234 ], "microsims": [ "nand-conversion-walkthrough" ] }, "230": { "id": 230, "label": "NOR-NOR Realization", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "A two-level circuit implementation in which a product-of-sums expression is realized entirely with NOR gates in place of OR and AND gates.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 57, 61, 85 ], "dependents": [ 231, 232, 234 ], "microsims": [] }, "231": { "id": 231, "label": "NAND-NOR Mixed Networks", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "Multi-level circuits that combine NAND and NOR gates to realize a function more efficiently than a single-gate-type implementation.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 229, 230 ], "dependents": [], "microsims": [ "nand-nor-converter" ] }, "232": { "id": 232, "label": "NOR-NAND Mixed Networks", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "Multi-level circuits built from a mixture of NOR and NAND gates, used when it reduces the total gate or level count.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 229, 230 ], "dependents": [], "microsims": [] }, "233": { "id": 233, "label": "Bubble Pushing Technique", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "A visual technique for converting circuits between gate types by systematically moving inversion bubbles through a circuit, applying De Morgan's theorem graphically at each gate boundary.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 56, 57, 77, 78 ], "dependents": [ 234 ], "microsims": [ "bubble-pushing-simulator" ] }, "234": { "id": 234, "label": "Gate-Level Transformation", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "The systematic conversion of a gate network from one logically equivalent form to another, such as AND/OR to NAND/NAND, using Boolean identities.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 229, 230, 233 ], "dependents": [], "microsims": [] }, "235": { "id": 235, "label": "AOI Gate", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "A complex CMOS gate that computes the complement of the OR of multiple AND terms in a single transistor structure, implementing functions of the form &overline;(AB + CD) with approximately one gate delay.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 52, 53, 56 ], "dependents": [ 237 ], "microsims": [] }, "236": { "id": 236, "label": "OAI Gate", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "A complex CMOS gate that computes the complement of the AND of multiple OR terms in a single transistor structure, implementing functions of the form &overline;((A+B)(C+D)) as the dual of the AOI gate.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 52, 53, 57 ], "dependents": [ 237 ], "microsims": [] }, "237": { "id": 237, "label": "AOI-OAI Circuit Forms", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "Circuit structures built from AND-OR-Invert and OR-AND-Invert gates that realize a two-level function in a single physical gate.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 227, 235, 236 ], "dependents": [], "microsims": [] }, "238": { "id": 238, "label": "Propagation Delay", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "The time required for a signal change at a gate input to produce a corresponding change at its output, measured from the input transition midpoint to the output transition midpoint.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 51, 93 ], "dependents": [ 239, 240, 296, 404 ], "microsims": [ "critical-path-delay-explorer" ] }, "239": { "id": 239, "label": "Gate Delay Model", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "The propagation delay through a single logic gate, typically measured in nanoseconds, used as the basic unit for calculating total circuit delay along signal paths.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 51, 238 ], "dependents": [ 240 ], "microsims": [] }, "240": { "id": 240, "label": "Critical Path Analysis", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "The longest signal propagation path from any primary input to any primary output in a circuit, measured in total gate delays, which determines the worst-case propagation delay of the entire circuit.", "chapter": 7, "chapterTitle": "Multi-Level Gate Circuits", "chapterDir": "unit7-multi-level-gates", "chapterUrl": "../../unit7-multi-level-gates/", "glossaryUrl": "../../unit7-multi-level-gates/glossary/", "quizUrl": "../../unit7-multi-level-gates/quiz/", "problemsUrl": "../../unit7-multi-level-gates/problems/", "challengeUrl": "../../unit7-multi-level-gates/challenge/", "prerequisites": [ 228, 238, 239 ], "dependents": [ 241, 249 ], "microsims": [ "critical-path-delay-explorer" ] }, "241": { "id": 241, "label": "Circuit Delay Optimization", "group": "MLEV", "category": "Multi-Level Circuits", "definition": "Restructuring a multi-level circuit's gates and levels to reduce its worst-case propagation delay.", "chapter": 7, "chapterTitle": "Multi-Level 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"glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 89, 252 ], "dependents": [ 254 ], "microsims": [] }, "254": { "id": 254, "label": "8-to-1 Multiplexer", "group": "CMOD", "category": "Combinational Modules", "definition": "A multiplexer with eight data inputs and three select lines that choose which one input is passed to the output.", "chapter": 8, "chapterTitle": "Combinational Logic Modules", "chapterDir": "unit8-combinational-modules", "chapterUrl": "../../unit8-combinational-modules/", "glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 89, 253 ], "dependents": [ 260 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"../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 84, 252, 255, 256 ], "dependents": [ 258 ], "microsims": [ "mux-function-walkthrough" ] }, "258": { "id": 258, "label": "MUX-Based Function Implementation", "group": "CMOD", "category": "Combinational Modules", "definition": "A design technique that implements an arbitrary Boolean function directly by wiring its truth table values to the data inputs of a multiplexer.", "chapter": 8, "chapterTitle": "Combinational Logic Modules", "chapterDir": "unit8-combinational-modules", "chapterUrl": "../../unit8-combinational-modules/", "glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 66, 95, 257 ], "dependents": [ 259, 260 ], "microsims": [] }, "259": { "id": 259, "label": "Shannon Expansion for MUX", "group": "CMOD", "category": "Combinational Modules", "definition": "The application of Shannon's expansion theorem to implement a Boolean function directly with a multiplexer, using the expansion variable as the select input and the cofactors as the data inputs.", "chapter": 8, "chapterTitle": "Combinational Logic Modules", "chapterDir": "unit8-combinational-modules", "chapterUrl": "../../unit8-combinational-modules/", "glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 155, 156, 258 ], "dependents": [ 260 ], "microsims": [ "mux-function-walkthrough" ] }, "260": { "id": 260, "label": "MUX Tree Implementation", "group": "CMOD", "category": "Combinational Modules", "definition": "A technique for building a multiplexer with more select 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"../../unit8-combinational-modules/", "glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 91, 93, 128 ], "dependents": [ 262, 266, 267, 270, 340 ], "microsims": [ "decoder-simulator" ] }, "262": { "id": 262, "label": "2-to-4 Decoder", "group": "CMOD", "category": "Combinational Modules", "definition": "A decoder with two inputs that activates exactly one of its four output lines based on the binary input code.", "chapter": 8, "chapterTitle": "Combinational Logic Modules", "chapterDir": "unit8-combinational-modules", "chapterUrl": "../../unit8-combinational-modules/", "glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": 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"glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 89, 263, 264 ], "dependents": [ 272, 275 ], "microsims": [] }, "266": { "id": 266, "label": "Decoder-Based Function Implementation", "group": "CMOD", "category": "Combinational Modules", "definition": "A design technique that implements a Boolean function by ORing together the decoder output lines corresponding to the function's minterms.", "chapter": 8, "chapterTitle": "Combinational Logic Modules", "chapterDir": "unit8-combinational-modules", "chapterUrl": "../../unit8-combinational-modules/", "glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": 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"../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 251, 261 ], "dependents": [ 274 ], "microsims": [] }, "271": { "id": 271, "label": "Magnitude Comparator Module", "group": "CMOD", "category": "Combinational Modules", "definition": "A circuit that compares two multi-bit binary numbers and outputs their relative magnitude relationship.", "chapter": 8, "chapterTitle": "Combinational Logic Modules", "chapterDir": "unit8-combinational-modules", "chapterUrl": "../../unit8-combinational-modules/", "glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 93, 113 ], "dependents": [ 272 ], "microsims": [ "magnitude-comparator" ] }, "272": { "id": 272, "label": "Cascading Comparators", "group": "CMOD", "category": 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"Combinational Logic Modules", "chapterDir": "unit8-combinational-modules", "chapterUrl": "../../unit8-combinational-modules/", "glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 60, 101 ], "dependents": [ 274, 353 ], "microsims": [ "tri-state-buffer-truth-table" ] }, "274": { "id": 274, "label": "Bus Architecture", "group": "CMOD", "category": "Combinational Modules", "definition": "A shared set of wires that multiple digital devices connect to, using tri-state outputs so only one device drives the bus at a time.", "chapter": 8, "chapterTitle": "Combinational Logic Modules", "chapterDir": "unit8-combinational-modules", "chapterUrl": "../../unit8-combinational-modules/", "glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 90, 101, 270, 273 ], "dependents": [], "microsims": [] }, "275": { "id": 275, "label": "Cascading Combinational Modules", "group": "CMOD", "category": "Combinational Modules", "definition": "Connecting multiple identical combinational modules, such as adders or comparators, to extend their function to a wider bit width.", "chapter": 8, "chapterTitle": "Combinational Logic Modules", "chapterDir": "unit8-combinational-modules", "chapterUrl": "../../unit8-combinational-modules/", "glossaryUrl": "../../unit8-combinational-modules/glossary/", "quizUrl": "../../unit8-combinational-modules/quiz/", "problemsUrl": "../../unit8-combinational-modules/problems/", "challengeUrl": "../../unit8-combinational-modules/challenge/", "prerequisites": [ 89, 90, 265, 272 ], "dependents": [], "microsims": [] }, "276": { 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"Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 276 ], "dependents": [ 299, 303 ], "microsims": [] }, "278": { "id": 278, "label": "Feedback Loop", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "A signal path in which a circuit's output is routed back to one of its inputs, creating the ability to sustain a state and providing the fundamental mechanism for memory in sequential circuits.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 51, 276 ], "dependents": [ 279, 280 ], "microsims": [] }, "279": { "id": 279, "label": "SR Latch (NOR)", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "An SR latch built from two cross-coupled NOR gates, where Set=1 forces Q=1 and Reset=1 forces Q=0, with S=R=0 holding the current state.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 57, 278 ], "dependents": [ 281, 282 ], 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"chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 100, 279 ], "dependents": [ 283 ], "microsims": [] }, "283": { "id": 283, "label": "D Latch", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "A level-sensitive memory element that passes its data input D directly to output Q while the enable signal is active (transparent mode) and holds the last captured value when the enable goes inactive.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": 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"challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 283 ], "dependents": [ 290 ], "microsims": [] }, "285": { "id": 285, "label": "Clock Signal", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "A periodic square wave that alternates between logic 0 and logic 1, serving as the timing reference that synchronizes all state changes in a synchronous sequential circuit.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 101, 276 ], "dependents": [ 286, 294, 295, 298, 300, 406, 409 ], "microsims": [] }, "286": { "id": 286, "label": "Clock Edge", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "The instant a clock signal transitions from one logic level to the other, either rising (0 to 1) or falling (1 to 0).", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 285 ], "dependents": [ 287, 293 ], "microsims": [] }, "287": { "id": 287, "label": "Edge Triggering", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "A flip-flop control scheme in which the output changes state only at the instant of a clock edge, rather than throughout the level of the clock.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 286 ], "dependents": [ 288, 289, 290 ], "microsims": [ "flipflop-timing-walkthrough" ] }, "288": { "id": 288, "label": "Positive Edge Trigger", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "A flip-flop triggering scheme in which state changes occur only on the rising (0-to-1) transition of the clock signal.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 287 ], "dependents": [ 290 ], "microsims": [] }, "289": { "id": 289, "label": "Negative Edge Trigger", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "A flip-flop triggering scheme in which state changes occur only on the falling (1-to-0) transition of the clock signal.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 287 ], "dependents": [ 293 ], "microsims": [] }, "290": { "id": 290, "label": "D Flip-Flop", "group": "SEQF", "category": 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provides four operations: hold (J=K=0), reset (J=0, K=1), set (J=1, K=0), and toggle (J=K=1), with the characteristic equation Q_next = JQ' + K'Q.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 281, 290 ], "dependents": [ 292 ], "microsims": [ "jk-flipflop-simulator" ] }, "292": { "id": 292, "label": "T Flip-Flop", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "An edge-triggered memory element with a single toggle input T that either holds the current state (T = 0) or complements it (T = 1) at each active clock edge, with the characteristic equation Q_next = T XOR Q.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 291 ], "dependents": [ 313 ], "microsims": [] }, "293": { "id": 293, "label": "Master-Slave Flip-Flop", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "A flip-flop constructed from two latches with complementary enables, where the master latch captures input data during one clock phase and the slave latch transfers it to the output during the opposite phase.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 286, 289, 290 ], "dependents": [ 294 ], "microsims": [] }, "294": { "id": 294, "label": "Setup Time", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "The minimum duration that a flip-flop's data input must be stable before the active clock edge arrives to ensure the value is correctly captured and stored.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 285, 290, 293 ], "dependents": [ 297, 404 ], "microsims": [ "setup-hold-metastability-explorer" ] }, "295": { "id": 295, "label": "Hold Time", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "The minimum duration that a flip-flop's data input must remain stable after the active clock edge to ensure the input value is correctly captured by the internal circuitry.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 285, 290 ], "dependents": [ 297, 404 ], "microsims": [ "setup-hold-metastability-explorer" ] }, "296": { "id": 296, "label": "Clock-to-Q Delay", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "The time elapsed from the active clock edge until the flip-flop output Q settles to its new valid logic level, representing the flip-flop's output propagation delay.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 238, 290 ], "dependents": [ 332 ], "microsims": [] }, "297": { "id": 297, "label": "Metastability", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "An unstable condition in which a flip-flop's output voltage hovers between valid logic 0 and logic 1 levels for an unpredictable duration, caused by violating setup or hold time requirements.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 294, 295 ], "dependents": [ 332 ], "microsims": [ "setup-hold-metastability-explorer" ] }, "298": { "id": 298, "label": "Synchronous Logic", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "Sequential logic in which all state changes are coordinated by a common clock signal.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 285, 290 ], "dependents": [ 306, 332 ], "microsims": [] }, "299": { "id": 299, "label": "Asynchronous Logic", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "Sequential logic in which state changes can occur at any time in response to input changes, without a common clock signal.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 276, 277 ], "dependents": [ 332 ], "microsims": [] }, "300": { "id": 300, "label": "Timing Diagram", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "A graphical representation showing the values of multiple digital signals plotted against a common time axis, used to analyze and verify the temporal behavior of sequential circuits.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 285, 290 ], "dependents": [ 332 ], "microsims": [ "timing-diagram-analyzer" ] }, "301": { "id": 301, "label": "Characteristic Table", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "A table that defines the next state of a flip-flop based on its current inputs and, for some types, the current state, describing the device's behavior from the perspective of \"given inputs, find next state.\"", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 64, 290 ], "dependents": [ 302 ], "microsims": [] }, "302": { "id": 302, "label": "Excitation Table", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "The inverse of a characteristic table, showing the required flip-flop input values to produce a desired state transition from a known current state, essential for sequential circuit design.", "chapter": 9, "chapterTitle": "Sequential Logic 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"../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 276, 277 ], "dependents": [ 304, 305, 308, 319 ], "microsims": [] }, "304": { "id": 304, "label": "Next State", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "The state a sequential circuit will transition to on the next active clock edge, determined by the current state and inputs.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 290, 303 ], "dependents": [ 305, 313 ], "microsims": [] }, "305": { "id": 305, "label": "State Transition", "group": "SEQF", "category": "Sequential Fundamentals", "definition": "A change from one state to another in a sequential circuit, occurring on a clock edge in response to the circuit's inputs.", "chapter": 9, "chapterTitle": "Sequential Logic Fundamentals", "chapterDir": "unit9-sequential-fundamentals", "chapterUrl": "../../unit9-sequential-fundamentals/", "glossaryUrl": "../../unit9-sequential-fundamentals/glossary/", "quizUrl": "../../unit9-sequential-fundamentals/quiz/", "problemsUrl": "../../unit9-sequential-fundamentals/problems/", "challengeUrl": "../../unit9-sequential-fundamentals/challenge/", "prerequisites": [ 303, 304 ], "dependents": [ 319, 320 ], "microsims": [] }, "306": { "id": 306, "label": "Register", "group": "SEQD", "category": "Sequential Design", "definition": "A group of flip-flops that stores a multi-bit binary word, with each flip-flop holding one bit, commonly used for temporary data storage, data transfer, and as building blocks in datapaths.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 290, 298 ], "dependents": [ 307, 308, 313, 398, 406 ], "microsims": [] }, "307": { "id": 307, "label": "Parallel Load Register", "group": "SEQD", "category": "Sequential Design", "definition": "A register that can accept all of its data bits simultaneously on a single clock edge when a load enable signal is asserted, allowing an entire n-bit word to be captured in one clock cycle.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": 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"dependents": [ 309, 310, 311, 312, 317, 409 ], "microsims": [ "shift-register-simulator", "shift-register-walkthrough" ] }, "309": { "id": 309, "label": "SISO Shift Register", "group": "SEQD", "category": "Sequential Design", "definition": "A shift register with a serial input and a serial output, shifting one bit in and one bit out each clock cycle.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 308 ], "dependents": [ 334 ], "microsims": [] }, "310": { "id": 310, "label": "SIPO Shift Register", "group": "SEQD", "category": "Sequential Design", "definition": "A shift register that accepts data one bit at a time on a serial input and makes all stored bits available simultaneously on parallel outputs.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 308 ], "dependents": [ 334 ], "microsims": [] }, "311": { "id": 311, "label": "PISO Shift Register", "group": "SEQD", "category": "Sequential Design", "definition": "A shift register that loads all bits simultaneously through parallel inputs and then shifts them out one bit at a time on a serial output.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 307, 308 ], "dependents": [ 334 ], "microsims": [] }, "312": { "id": 312, "label": "PIPO Shift Register", "group": "SEQD", "category": "Sequential Design", "definition": "A shift register that loads all bits simultaneously through parallel inputs and outputs all bits simultaneously through parallel outputs, functioning as a simple register.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 307, 308 ], "dependents": [ 334 ], "microsims": [] }, "313": { "id": 313, "label": "Binary Up Counter", "group": "SEQD", "category": "Sequential Design", "definition": "A sequential circuit composed of flip-flops that advances through its count sequence in increasing numerical order on each active clock edge.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 292, 304, 306 ], "dependents": [ 314, 315, 316, 398 ], "microsims": [ "counter-simulator" ] }, "314": { "id": 314, "label": "Binary Down Counter", "group": "SEQD", "category": "Sequential Design", "definition": "A sequential circuit composed of flip-flops that advances through its count sequence in decreasing numerical order on each active clock edge.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 313 ], "dependents": [ 315 ], "microsims": [ "counter-simulator" ] }, "315": { "id": 315, "label": "Up-Down Counter", "group": "SEQD", "category": "Sequential Design", "definition": "A sequential circuit that progresses through a defined sequence of states in response to clock pulses, used for counting events, generating timing signals, or producing specific binary output patterns.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 313, 314 ], "dependents": [ 333 ], "microsims": [ "counter-simulator" ] }, "316": { "id": 316, "label": "Modulo-N Counter", "group": "SEQD", "category": "Sequential Design", "definition": "A counter that cycles through exactly N distinct states before returning to its initial state, achieved either by using an N-state natural binary sequence or by adding reset logic to a larger counter.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 95, 313 ], "dependents": [ 317, 333 ], "microsims": [ "counter-simulator" ] }, "317": { "id": 317, "label": "Ring Counter", "group": "SEQD", "category": "Sequential Design", "definition": "A circular shift register where the output of the last flip-flop feeds directly back to the input of the first, with a single 1 circulating through n flip-flops to produce n unique one-hot encoded states.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 308, 316 ], "dependents": [ 318 ], "microsims": [ "counter-simulator" ] }, "318": { "id": 318, "label": "Johnson Counter", "group": "SEQD", "category": "Sequential Design", "definition": "A shift register counter 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"chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 303, 305 ], "dependents": [ 320, 321, 322, 323, 395, 399, 403 ], "microsims": [ "fsm-designer" ] }, "320": { "id": 320, "label": "State Diagram", "group": "SEQD", "category": "Sequential Design", "definition": "A directed graph representation of a finite state machine where nodes represent states and labeled arcs represent transitions, showing the input conditions and output values associated with each transition or state.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": 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"../../unit10-sequential-design/challenge/", "prerequisites": [ 64, 319 ], "dependents": [ 324, 328, 331, 403 ], "microsims": [] }, "322": { "id": 322, "label": "Moore Machine", "group": "SEQD", "category": "Sequential Design", "definition": "A finite state machine whose output depends solely on the current state and is independent of the current input, producing outputs that change only on clock edges when the state transitions.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 319, 320 ], "dependents": [ 330 ], "microsims": [ "moore-mealy-comparison" ] }, "323": { "id": 323, "label": "Mealy Machine", "group": "SEQD", "category": "Sequential Design", "definition": "A finite state machine whose output depends on both the current state and the current input, allowing outputs to change asynchronously within a clock period in response to input changes.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 319, 320 ], "dependents": [ 331 ], "microsims": [ "moore-mealy-comparison" ] }, "324": { "id": 324, "label": "State Assignment", "group": "SEQD", "category": "Sequential Design", "definition": "The process of assigning unique binary codes to each state in a finite state machine, directly affecting the complexity of the next-state and output combinational logic in the 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"SEQD", "category": "Sequential Design", "definition": "An FSM state assignment scheme in which adjacent states differ by only one bit, reducing output glitches during state transitions.", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 324, 325 ], "dependents": [ 328 ], "microsims": [ "binary-gray-converter" ] }, "328": { "id": 328, "label": "State Minimization", "group": "SEQD", "category": "Sequential Design", "definition": "The process of reducing the number of states in a finite state machine by identifying and merging equivalent states, producing a minimal-state machine that exhibits identical input-output behavior.", "chapter": 10, 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"../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 302, 324 ], "dependents": [ 330, 331 ], "microsims": [] }, "330": { "id": 330, "label": "Output Logic", "group": "SEQD", "category": "Sequential Design", "definition": "The combinational logic block in a sequential circuit that generates the circuit's outputs from the current state (Moore) or from the current state and inputs (Mealy).", "chapter": 10, "chapterTitle": "Sequential Circuit Design", "chapterDir": "unit10-sequential-design", "chapterUrl": "../../unit10-sequential-design/", "glossaryUrl": "../../unit10-sequential-design/glossary/", "quizUrl": "../../unit10-sequential-design/quiz/", "problemsUrl": "../../unit10-sequential-design/problems/", "challengeUrl": "../../unit10-sequential-design/challenge/", "prerequisites": [ 322, 329 ], "dependents": [ 331 ], "microsims": [] }, "331": { "id": 331, "label": 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