Glossary: Programmable Logic Devices

Key terms and definitions for Unit 11. Definitions follow ISO 11179 metadata registry standards.

A

Antifuse — A one-time programmable interconnect element that is initially an open circuit and becomes a permanent low-resistance connection when a high programming voltage is applied, the inverse of a conventional fuse.

B

Bitstream — A binary configuration file that is loaded into an FPGA to define the logic functions, interconnect routing, and I/O pin assignments, effectively programming the device to implement a specific digital design.

C

Complex PLD — A programmable logic device that combines multiple SPLD-equivalent function blocks with a programmable interconnect matrix on a single chip, providing higher logic capacity than a simple PLD while remaining non-volatile.

Configurable Logic Block — The fundamental programmable logic element within an FPGA, typically containing lookup tables, flip-flops, and multiplexers, that can be configured to implement arbitrary combinational and sequential logic functions.

E

EEPROM — Electrically Erasable Programmable Read-Only Memory, a non-volatile memory technology that can be electrically erased and reprogrammed at the byte level, commonly used in PLDs to allow in-system reconfiguration.

EPROM — Erasable Programmable Read-Only Memory, a non-volatile memory technology that is programmed electrically and erased by exposure to ultraviolet light through a quartz window on the chip package, requiring physical removal for erasure.

F

Field-Programmable Gate Array — An integrated circuit containing an array of configurable logic blocks, programmable interconnects, and I/O blocks that can be configured by the end user to implement virtually any digital circuit after manufacturing.

Flash Memory — A non-volatile memory technology based on floating-gate transistors that can be electrically erased in blocks and reprogrammed, used in some FPGAs and CPLDs to store configuration data that persists without external power.

Function Block — A major logic subdivision within a CPLD, typically equivalent to one SPLD, containing a programmable AND array, product-term allocators, and macrocells that collectively implement a portion of the overall design.

Fuse — A one-time programmable interconnect element that is initially a closed connection and becomes a permanent open circuit when a high programming current melts the conductive link, used in early PLDs such as PROMs and PALs.

G

GAL — Generic Array Logic, a reprogrammable PLD with a programmable AND array and fixed OR array that uses EEPROM technology, allowing it to be electrically erased and reprogrammed multiple times as a replacement for various PAL devices.

H

Hardware Description Language — A specialized programming language used to describe the structure and behavior of digital circuits at various levels of abstraction, enabling simulation, synthesis, and implementation of digital designs in FPGAs and ASICs.

L

Lookup Table — A small programmable memory within an FPGA configurable logic block that stores the truth table of a Boolean function, enabling implementation of any logic function of its input variables by reading the stored output value.

M

Macrocell — The output structure within a PLD or CPLD function block that typically includes a configurable flip-flop, output enable control, and polarity selection, providing either registered or combinational output for each function block output.

Mask ROM — A read-only memory whose data content is permanently defined during the semiconductor fabrication process through a custom photolithographic mask, making it the lowest cost per unit at high volumes but inflexible after manufacture.

N

Non-Recurring Engineering Cost — The one-time design, development, and tooling expenses incurred before production begins, including mask generation, verification, and testing setup, which must be amortized across all manufactured units of the final product.

O

One-Time Programmable — A category of programmable devices that can be configured only once because their programming mechanism permanently alters the physical structure, such as blowing fuses or forming antifuses, making reprogramming impossible.

P

PAL — Programmable Array Logic, a simple PLD architecture featuring a programmable AND array followed by a fixed OR array, where each output is a sum of a fixed number of programmable product terms, simpler than a PLA.

Partial Reconfiguration — The capability to modify a portion of an FPGA's configuration while the remaining logic continues to operate without interruption, enabling dynamic hardware adaptation and time-multiplexing of FPGA resources.

PLA — Programmable Logic Array, a PLD architecture with both a programmable AND array and a programmable OR array, providing maximum flexibility in implementing sum-of-products expressions since any product term can be shared among any output.

PLA AND Plane — The programmable AND array in a PLA that generates product terms by forming programmable connections between input variables and their complements to AND gates, defining which literals appear in each product term.

PLA OR Plane — The programmable OR array in a PLA that combines selected product terms from the AND plane by forming programmable connections to OR gates, determining which product terms contribute to each output function.

Place and Route — The physical implementation stage where synthesized logic elements are assigned to specific locations on an FPGA or ASIC die (placement) and interconnected through routing resources to meet timing and area constraints.

Programmable Interconnect — A configurable routing network within a CPLD or FPGA that provides signal paths between logic blocks, I/O pins, and other resources, whose connections are established through programmable switch elements.

Programmable Logic Device — A general term for any integrated circuit that contains uncommitted logic which can be configured by the user after manufacturing to implement custom digital functions, encompassing SPLDs, CPLDs, and FPGAs.

PROM — Programmable Read-Only Memory, a memory device that is manufactured with all fuses intact and programmed once by the user by selectively blowing fuses to store a permanent bit pattern, functioning as a complete decoder for logic implementation.

R

Read-Only Memory — A non-volatile memory device that permanently or semi-permanently stores data, addressed by input lines that select a word location whose pre-stored contents appear at the data outputs, usable for logic function implementation.

Register-Transfer Level — A level of hardware abstraction that describes a digital circuit in terms of data transfers between registers and the combinational logic transformations applied during those transfers on each clock cycle.

S

Simple PLD — A single-chip programmable logic device consisting of a single AND-OR array structure, such as a PAL, PLA, or GAL, capable of implementing moderately complex combinational and simple sequential logic functions.

SRAM-Based Configuration — An FPGA programming technology where static RAM cells control the configuration of logic blocks and interconnect switches, offering unlimited reprogrammability but requiring the configuration to be reloaded from external memory at each power-up.

Static Timing Analysis — A method of verifying circuit timing by computing worst-case signal propagation delays through all combinational paths without requiring simulation vectors, checking that setup and hold constraints are met at every flip-flop.

T

Technology Mapping — The process of converting a technology-independent optimized Boolean network into a circuit that uses gates from a specific standard cell library, balancing area, delay, and power.