Glossary: Introduction to VHDL

Key terms and definitions for Unit 12. Definitions follow ISO 11179 metadata registry standards.

A

Architecture Body — The section of a VHDL design unit that describes the internal behavior, structure, or dataflow implementation of an entity. It specifies how the entity's ports relate to one another through signals, processes, and component instantiations.

Assert Statement — A VHDL simulation construct that evaluates a Boolean condition and triggers a report message with a specified severity level (note, warning, error, or failure) when the condition is false, used in testbenches for automated verification.

B

Behavioral Modeling — A VHDL description style that specifies circuit function using sequential statements within processes, resembling software algorithms, without explicitly defining the underlying hardware structure or gate-level connections.

C

Case Statement — A sequential VHDL statement inside a process that selects one of several execution paths based on the value of a single expression, analogous to a truth table or selection mechanism in hardware.

Code Coverage — A verification metric that measures which portions of the HDL source code have been exercised during simulation, including statement, branch, condition, and expression coverage, to assess testbench thoroughness.

Concurrent Signal Assignment — A VHDL statement that exists outside a process and continuously drives a signal based on an expression. All concurrent assignments execute simultaneously, modeling the parallel nature of hardware.

Conditional Signal Assignment — A concurrent VHDL statement that assigns a signal value based on a prioritized chain of Boolean conditions, implementing priority-encoded logic similar to an if-then-else chain.

D

Dataflow Modeling — A VHDL description style that uses concurrent signal assignment statements to describe how data flows through combinational logic, specifying Boolean equations and transformations without explicit structural or sequential constructs.

Default Assignment — A signal assignment placed before conditional or case logic within a process to ensure the signal receives a defined value on every execution path, preventing unintended latch inference during synthesis.

Delta Delay — An infinitesimally small simulation time step in VHDL used to order signal updates and process evaluations within the same simulation time, ensuring correct cause-and-effect sequencing without advancing wall-clock time.

Design Hierarchy — The multi-level organizational structure of a digital system where a top-level module instantiates sub-modules, which in turn instantiate lower-level components, forming a tree of progressively simpler design units.

Design Modularity — A design principle that partitions a system into self-contained, well-defined functional blocks with clear interfaces, enabling independent development, testing, reuse, and substitution of individual modules.

Design Under Test — The specific VHDL entity and architecture being verified by a testbench. It is the target module instantiated within the testbench environment that receives stimulus and whose outputs are observed for correctness.

E

Entity Declaration — A VHDL construct that defines the external interface of a design unit, specifying its name and ports with their directions and data types, without revealing any internal implementation details.

Enumerated Type — A user-defined VHDL data type consisting of an explicitly listed set of named values, commonly used to represent finite-state machine states in a readable and self-documenting manner.

F

Field-Programmable Gate Array — An integrated circuit containing an array of configurable logic blocks, programmable interconnects, and I/O blocks that can be configured by the end user to implement virtually any digital circuit after manufacturing.

Functional Verification — The process of confirming through simulation, formal methods, or emulation that a digital design behaves according to its specification under all relevant input conditions before fabrication or FPGA implementation.

G

Gray Code Encoding — A state encoding scheme for finite state machines where adjacent states differ by exactly one bit, minimizing switching activity during state transitions and reducing dynamic power consumption and glitch hazards.

H

Hardware Description Language — A specialized programming language used to describe the structure and behavior of digital circuits at various levels of abstraction, enabling simulation, synthesis, and implementation of digital designs in FPGAs and ASICs.

Hardware Inference — The process by which a synthesis tool interprets VHDL behavioral descriptions and determines the corresponding hardware structures, such as multiplexers, registers, or adders, to implement in the target technology.

I

If-Then-Else Statement — A sequential VHDL statement used within a process that evaluates conditions in priority order and executes the corresponding statements for the first true condition, synthesizing into priority-encoded logic.

L

Latch Inference — An unintended synthesis outcome where a level-sensitive latch is generated because a signal is not assigned a value on every possible execution path through a combinational process, creating implicit memory.

O

One-Hot Encoding — A state encoding scheme for finite state machines that assigns one flip-flop per state, with exactly one flip-flop set to '1' at any time, simplifying next-state logic at the cost of additional registers.

P

Port — A named interface element in a VHDL entity declaration that defines a connection point for signals entering or leaving the design unit, characterized by a name, data type, and directional mode.

Port Mode — A VHDL keyword specifying the direction of data flow through a port: in for input-only, out for output-only, inout for bidirectional, or buffer for an output that can be internally read.

Process Statement — A VHDL concurrent construct containing sequential statements that execute in the order listed. A process activates when any signal in its sensitivity list changes, modeling both combinational and sequential logic.

R

Register-Transfer Level — A level of hardware abstraction that describes a digital circuit in terms of data transfers between registers and the combinational logic transformations applied during those transfers on each clock cycle.

S

Selected Signal Assignment — A concurrent VHDL statement that assigns a signal value based on matching a selector expression to specific choices, functioning like a parallel case statement outside a process.

Self-Checking Testbench — A testbench that automatically compares the design under test's outputs against expected values or a reference model within the simulation, reporting pass or fail without requiring manual waveform inspection.

Sensitivity List — A list of signals in a process declaration header that specifies which signal changes trigger re-evaluation of the process. An incomplete sensitivity list can cause simulation and synthesis mismatches.

Signal — A VHDL object that represents a physical wire or connection carrying a value over time. Signals have associated scheduling semantics where assignments take effect after a delta delay, not immediately.

std_logic — A nine-valued enumerated type from the IEEE 1164 standard representing a single digital wire. Values include '0', '1', 'Z' for high-impedance, 'X' for unknown, and 'U' for uninitialized, among others.

std_logic_vector — An array type of std_logic elements from the IEEE 1164 standard, used to represent multi-bit buses and data words. It supports both ascending (to) and descending (downto) index ranges.

Structural Modeling — A VHDL description style that builds a design by instantiating and interconnecting lower-level components, explicitly defining the hardware hierarchy and wiring topology analogous to a schematic netlist.

Synthesizable Subset — The restricted portion of the VHDL language that synthesis tools can translate into actual hardware. Constructs like file I/O, wait for specific times, and after-delay clauses are excluded from this subset.

T

Testbench — A non-synthesizable VHDL entity with no ports that instantiates the design under test, generates stimulus signals, and optionally checks output correctness to verify the design through simulation.

Top-Down Design — A systematic design methodology that begins with the highest-level system specification and progressively decomposes it into smaller, more detailed sub-modules until each block is simple enough to implement directly.

V

VHDL — VHSIC Hardware Description Language, a standardized IEEE language (IEEE 1076) used to describe, simulate, and synthesize digital electronic systems at multiple levels of abstraction from behavioral to structural.

Variable — A VHDL object declared within a process that stores intermediate computation values. Unlike signals, variables update immediately upon assignment and are not visible outside the declaring process.

VHDL Design Unit — A self-contained, independently compilable section of VHDL source code. The five types are entity declarations, architecture bodies, package declarations, package bodies, and configuration declarations.