Glossary: System Integration and Design

Key terms and definitions for Unit 13. Definitions follow ISO 11179 metadata registry standards.

A

ALU — Arithmetic Logic Unit, a combinational digital circuit that performs arithmetic operations such as addition and subtraction, and bitwise logical operations such as AND, OR, and XOR, based on a function-select input.

C

Bus Arbitration — The process of resolving contention when multiple modules request access to a shared communication bus simultaneously, using priority-based, round-robin, or daisy-chain arbitration schemes to grant bus access to one requester at a time.

Clock Domain Crossing — The interface boundary where a signal generated in one clock domain is sampled by logic operating in a different clock domain, requiring synchronization to prevent metastability and data corruption.

Clock-to-Q Delay — The time elapsed from the active clock edge until the flip-flop output Q settles to its new valid logic level, representing the flip-flop's output propagation delay.

Clock Gating — A power reduction technique that disables the clock signal to inactive circuit modules, eliminating unnecessary flip-flop toggling and reducing dynamic power consumption, typically implemented using vendor-specific clock buffer primitives on FPGAs.

Code Coverage — A verification metric that measures which portions of the HDL source code have been exercised during simulation, including statement, branch, condition, and expression coverage, to assess testbench thoroughness.

Control Signal — A digital signal that directs or modifies the operation of a circuit or system.

Control Unit — A sequential circuit, typically a finite-state machine, that generates timing and control signals to coordinate the operations of the datapath, memory, and I/O subsystems according to a defined instruction sequence.

Critical Path — The longest signal propagation path from any input to the output in a logic circuit, which determines the circuit's maximum operating speed.

D

Data Forwarding — A pipeline hazard resolution technique that bypasses the normal register write-back path by routing a computed result directly from a later pipeline stage back to an earlier stage's input, avoiding the need to stall the pipeline while waiting for the result to be written to the register file.

Datapath — The portion of a digital system containing functional units such as registers, multiplexers, ALUs, and buses that perform data storage, transfer, and transformation operations under the direction of the control unit.

Dynamic Power — The component of power dissipation in CMOS circuits caused by charging and discharging load capacitances during logic transitions, governed by P = αCV²f where α is switching activity, C is capacitance, V is supply voltage, and f is clock frequency.

Design for Testability — A collection of design techniques and added circuitry that make a manufactured integrated circuit easier to test by improving controllability and observability of internal nodes after fabrication.

Design Hierarchy — The multi-level organizational structure of a digital system where a top-level module instantiates sub-modules, which in turn instantiate lower-level components, forming a tree of progressively simpler design units.

Design Modularity — A design principle that partitions a system into self-contained, well-defined functional blocks with clear interfaces, enabling independent development, testing, reuse, and substitution of individual modules.

Design Under Test — The specific VHDL entity and architecture being verified by a testbench. It is the target module instantiated within the testbench environment that receives stimulus and whose outputs are observed for correctness.

F

Finite State Machine — A mathematical model of sequential computation consisting of a finite set of states, input and output alphabets, a next-state function, and an output function, used to design synchronous sequential circuits.

Functional Verification — The process of confirming through simulation, formal methods, or emulation that a digital design behaves according to its specification under all relevant input conditions before fabrication or FPGA implementation.

H

Hold Time — The minimum duration that a flip-flop's data input must remain stable after the active clock edge to ensure the input value is correctly captured by the internal circuitry.

Hold Time Budgeting — The timing analysis practice of ensuring that data at a flip-flop's input remains stable for a sufficient duration after the active clock edge, accounting for minimum clock-to-output delays and routing variations.

I

Interface Specification — A formal document or definition that describes the signals, timing, protocols, and data formats required for two modules or subsystems to communicate correctly, establishing a contract between design teams.

M

Mealy Machine — A finite state machine whose output depends on both the current state and the current input, allowing outputs to change asynchronously within a clock period in response to input changes.

Metastability — An unstable condition in which a flip-flop's output voltage hovers between valid logic 0 and logic 1 levels for an unpredictable duration, caused by violating setup or hold time requirements.

Moore Machine — A finite state machine whose output depends solely on the current state and is independent of the current input, producing outputs that change only on clock edges when the state transitions.

N

Non-Recurring Engineering Cost — The one-time design, development, and tooling expenses incurred before production begins, including mask generation, verification, and testing setup, which must be amortized across all manufactured units of the final product.

P

Pipeline Hazard — A situation in a pipelined design where the next instruction or operation cannot execute in the expected clock cycle due to a data dependency (data hazard), a control flow change (control hazard), or a resource conflict (structural hazard), requiring stalls, forwarding, or speculation to resolve.

Pipelining — A design technique that divides a combinational logic path into multiple stages separated by registers, allowing each stage to process different data simultaneously, thereby increasing clock frequency and throughput at the cost of latency.

Place and Route — The physical implementation stage where synthesized logic elements are assigned to specific locations on an FPGA or ASIC die (placement) and interconnected through routing resources to meet timing and area constraints.

Propagation Delay — The time required for a signal change at a gate's input to produce a corresponding change at its output, measured from the input transition to the output reaching a valid logic level.

R

Ready-Valid Handshake — A flow-control protocol where a sender asserts a valid signal to indicate data availability and a receiver asserts a ready signal to indicate acceptance capability. Data transfers only when both signals are asserted simultaneously.

Register — A group of flip-flops that stores a multi-bit binary word, with each flip-flop holding one bit, commonly used for temporary data storage, data transfer, and as building blocks in datapaths.

Register-Transfer Level — A level of hardware abstraction that describes a digital circuit in terms of data transfers between registers and the combinational logic transformations applied during those transfers on each clock cycle.

Resource Sharing — A synthesis optimization technique where a single hardware functional unit, such as an adder or multiplier, is time-multiplexed to perform operations for different data paths, reducing total area at the cost of additional control logic.

S

Scan Chain — A design-for-testability structure where all flip-flops in a circuit are connected into one or more serial shift registers during test mode, allowing external loading and unloading of internal state for manufacturing test.

Self-Checking Testbench — A testbench that automatically compares the design under test's outputs against expected values or a reference model within the simulation, reporting pass or fail without requiring manual waveform inspection.

Setup Time — The minimum duration that a flip-flop's data input must be stable before the active clock edge arrives to ensure the value is correctly captured and stored.

Setup Time Budgeting — The timing analysis practice of ensuring that data arrives and stabilizes at a flip-flop's input sufficiently before the active clock edge, accounting for clock period, combinational path delay, clock skew, and the flip-flop's setup requirement.

Static Timing Analysis — A method of verifying circuit timing by computing worst-case signal propagation delays through all combinational paths without requiring simulation vectors, checking that setup and hold constraints are met at every flip-flop.

Synchronizer Chain — A series of two or more flip-flops clocked by the same clock signal, used to safely sample an asynchronous input by allowing one full clock period for metastability resolution between stages.

System Partitioning — The process of dividing a complex digital system into distinct functional blocks or subsystems with well-defined interfaces, guided by considerations of functionality, timing, technology, and design team organization.

T

Test Vector — A specific set of input values applied to a circuit during testing or simulation, paired with the corresponding expected output values, used to verify that the circuit produces correct results for that input combination.

Testbench — A non-synthesizable VHDL entity with no ports that instantiates the design under test, generates stimulus signals, and optionally checks output correctness to verify the design through simulation.

Throughput — The rate at which a digital system produces valid output results, typically measured in operations per second or data units per clock cycle, reflecting the system's sustained processing capacity.

Top-Down Design — A systematic design methodology that begins with the highest-level system specification and progressively decomposes it into smaller, more detailed sub-modules until each block is simple enough to implement directly.

U

UART — Universal Asynchronous Receiver-Transmitter, a serial communication peripheral that converts parallel data to a serial bit stream for transmission and serial data back to parallel form on reception, without requiring a shared clock.

V

Verification Planning — The systematic process of defining verification goals, strategies, coverage metrics, testbench architecture, and required test scenarios before beginning simulation, ensuring comprehensive and organized design validation.