References: Unit 13 — System Integration and Design Projects

  1. Top-down and bottom-up design — Wikipedia — Overview of hierarchical design methodologies covering decomposition strategies, modular design principles, and their application in digital system engineering.
  2. Datapath — Wikipedia — Explanation of datapath architecture including registers, ALUs, multiplexers, and buses, with coverage of datapath-controller separation in digital system design.
  3. Static timing analysis — Wikipedia — Comprehensive coverage of STA including setup time, hold time, clock-to-q delay, critical path analysis, and maximum clock frequency calculation.
  4. Digital Design (6th Edition) — M. Morris Mano, Michael D. Ciletti — Pearson — Final chapters cover system-level design integrating combinational and sequential components into complete digital systems with verification strategies.
  5. Computer Organization and Design (6th Edition) — David A. Patterson, John L. Hennessy — Morgan Kaufmann — Classic textbook covering datapath and control unit design, pipelining, and system-level integration of digital components with emphasis on design trade-offs.
  6. Pipeline (computing) — Wikipedia — Detailed explanation of pipelining concepts including throughput vs latency trade-offs, pipeline hazards, and applications in digital hardware design.
  7. Universal asynchronous receiver-transmitter — Wikipedia — Coverage of UART protocol including frame format, baud rate, start/stop bits, parity, and shift register implementation for serial communication.
  8. Algorithmic state machine — Wikipedia — Explanation of ASM charts as a design tool for digital controllers, covering state boxes, decision boxes, and conditional output boxes for FSM specification.
  9. Design for testability — Wikipedia — Overview of DFT techniques including scan chains, built-in self-test (BIST), and boundary scan (JTAG) for ensuring manufactured digital circuits can be verified.
  10. Clock skew — Wikipedia — Explanation of clock distribution challenges including positive and negative skew, their effects on setup and hold timing margins, and mitigation techniques.