Glossary: Applications of Boolean Algebra

Key terms and definitions for Unit 3. Definitions follow ISO 11179 metadata registry standards.

A

Active-High / Active-Low — A convention describing whether a signal is asserted when it is logic 1 (active-high) or logic 0 (active-low), commonly relevant in seven-segment display decoder design.

Adder-Subtractor Circuit — A combinational circuit that uses a shared set of full adders with XOR gates and a mode control signal M to perform either binary addition (M=0) or two's complement subtraction (M=1) on multi-bit operands.

B

BCD (Binary Coded Decimal) — A binary encoding scheme in which each decimal digit (0–9) is represented by its own 4-bit binary equivalent, preserving decimal place-value structure at the cost of six unused codes per digit.

BCD Adder — A circuit that adds two BCD digits and applies a correction factor of 6 (0110) whenever the binary sum exceeds 9 or produces a carry out, ensuring the result remains valid BCD.

BCD to Binary Converter — A code conversion circuit that translates a BCD representation into pure binary by multiplying the tens digit by ten and adding the units digit, requiring multiplier and adder sub-circuits.

Binary to Gray Converter — A circuit that converts a standard binary number to Gray code by keeping the MSB unchanged and XORing each pair of adjacent binary bits to produce the remaining Gray code bits.

Borrow Bit — The output of a subtractor circuit that indicates when the minuend bit is smaller than the subtrahend bit (plus any incoming borrow), requiring a borrow from the next higher bit position.

C

Carry Bit — The output of an adder circuit that represents the overflow from adding bits in a single column, to be propagated to the next more significant bit position.

Carry-Lookahead Adder (CLA) — An adder architecture that computes all carry bits simultaneously using generate and propagate signals, eliminating the sequential carry propagation delay of ripple carry adders and achieving logarithmic rather than linear delay growth with operand width.

Circuit Analysis — The process of starting with an existing logic circuit and determining its behavior by deriving its Boolean expression and truth table from the gate-level connections.

Circuit Synthesis — The process of starting with a behavioral specification and creating a logic circuit that implements it, following the systematic design flow of truth table, Boolean expression, simplification, and gate implementation.

Code Converter — A combinational circuit that translates data from one binary representation (such as BCD, Gray code, or Excess-3) to another, enabling interoperability between subsystems that use different encoding schemes.

Combinational Logic — A category of digital circuits whose outputs depend solely on the current values of the inputs, with no memory of past states, so the same input combination always produces the same output.

Comparator Circuit — A combinational circuit that determines the relative magnitude relationship (greater than, less than, or equal) between two binary numbers by comparing corresponding bits from the most significant to the least significant.

Control Signal — A binary input that selects between different operating modes of a circuit, such as choosing between addition and subtraction in an adder-subtractor.

D

Difference Bit — The output of a subtractor circuit that represents the result of subtracting one bit from another, computed as the XOR of the inputs and any incoming borrow.

Don't Care Condition — An input combination in a truth table (marked X or d) for which the output can be freely assigned either 0 or 1 during optimization, because the combination either cannot occur or its output is irrelevant to the application.

E

Enable Signal — A control input that, when active (typically 1), permits a circuit to operate normally and, when inactive (0), forces all outputs to a disabled state regardless of other inputs.

Even Parity — An error-detection scheme in which the parity bit is chosen so that the total number of 1-bits in the data word (including the parity bit itself) is even.

Excess-3 Code — A BCD-related code in which each decimal digit is represented by its binary value plus three, useful because it is self-complementing (the nines' complement of a digit is obtained by inverting all bits).

F

Full Adder — A combinational circuit that adds three single-bit inputs (two operand bits A and B plus a carry-in from a previous stage) and produces a sum bit and a carry-out bit, enabling multi-bit cascaded addition.

Full Subtractor — A combinational circuit that subtracts one bit from another while accounting for a borrow-in from a previous stage, producing a difference bit and a borrow-out bit for cascaded multi-bit subtraction.

G

Generate Signal — In a carry-lookahead adder, the signal G_i = A_i · B_i indicating that bit position i produces a carry output regardless of the incoming carry, because both inputs are 1.

Gray Code — A binary encoding in which consecutive values differ in exactly one bit position, eliminating ambiguous intermediate readings in applications such as rotary position encoders and providing the ordering used in Karnaugh maps.

Gray to Binary Converter — A circuit that converts a Gray code number back to standard binary by keeping the MSB unchanged and XORing each Gray code bit with the previously recovered binary bit.

H

Hamming Code — An error-correcting code that uses multiple parity bits, each covering a specific subset of data bits, enabling the receiver to detect and correct single-bit errors by analyzing which parity checks fail to form a syndrome pointing to the error position.

Half Adder — A combinational circuit that adds two single-bit inputs and produces a sum bit (via XOR) and a carry bit (via AND), called "half" because it has no carry-in and cannot be directly cascaded for multi-bit addition.

Half Subtractor — A combinational circuit that subtracts one single-bit input B from another A, producing a difference bit (\(A \oplus B\)) and a borrow bit (\(\overline{A} \cdot B\)), without accounting for an incoming borrow from a prior stage.

I

Incompletely Specified Function — A Boolean function for which some input combinations have undefined or irrelevant outputs (don't cares), allowing the designer to choose output values that yield the simplest possible circuit implementation.

M

Magnitude Comparator — A multi-bit comparator circuit that compares two \(n\)-bit binary numbers and produces three outputs indicating whether the first number is greater than, less than, or equal to the second.

O

Odd Parity — An error-detection scheme in which the parity bit is chosen so that the total number of 1-bits in the data word (including the parity bit itself) is odd.

Overflow Detection — A technique for detecting signed arithmetic overflow by comparing the carry into the most significant bit (C_{n-1}) with the carry out (C_n); overflow is indicated when these two carries differ, computed as V = C_{n-1} XOR C_n.

P

Propagate Signal — In a carry-lookahead adder, the signal P_i = A_i XOR B_i indicating that bit position i will pass an incoming carry through to the output, enabling parallel carry computation across all bit positions.

Parity — A simple error-detection property based on counting the number of 1-bits in a data word; it can detect any single-bit error but cannot detect an even number of simultaneous bit errors.

Parity Checker — A circuit that receives a data word together with its parity bit and XORs all bits together, outputting a 1 (error detected) if the total parity does not match the expected convention.

Parity Generator — A circuit that computes a parity bit for a given data word by XORing all data bits together, producing the bit needed to establish even or odd parity for error detection during transmission.

Priority Encoder — A combinational circuit that accepts multiple input lines and outputs the binary code corresponding to the highest-priority active input, ignoring all lower-priority inputs that are simultaneously asserted.

Propagation Delay — The time required for a signal change at a gate's input to produce the corresponding change at its output, which accumulates through cascaded stages and determines the worst-case speed of circuits like ripple carry adders.

R

Ripple Carry Adder — A multi-bit adder constructed by chaining \(n\) full adders in series, where the carry-out of each stage connects to the carry-in of the next, causing carries to "ripple" sequentially from LSB to MSB.

S

Sequential Logic — A category of digital circuits whose outputs depend on both the current inputs and the circuit's stored internal state (history), requiring memory elements such as flip-flops and typically operating under clock synchronization.

Seven-Segment Decoder — A combinational circuit that converts a 4-bit BCD input into seven output signals (a through g), each controlling one segment of a seven-segment display to form a visible decimal digit.

Seven-Segment Display — An output device consisting of seven independently controlled LED segments (labeled a through g) arranged in a figure-eight pattern, capable of displaying decimal digits 0–9 and selected letters.

Sum Bit — The lower-order output of an adder circuit, representing the single-bit arithmetic sum of the input bits at a given position (computed as the XOR of the inputs and any carry-in).

Switching Function — The formal name for a Boolean function that describes the input-output behavior of a digital circuit, mapping combinations of binary input values to binary output values.

T

Two's Complement — A method for representing signed binary numbers in which the negative of a number is obtained by complementing all bits and adding one, enabling subtraction to be performed using addition hardware.

W

Word Problem to Boolean Conversion — The engineering skill of translating a natural-language specification into a precise Boolean expression by identifying input/output variables and mapping English logical phrases to their corresponding Boolean operators.

X

XNOR (Exclusive NOR) — A Boolean operation that outputs 1 when its two inputs are the same and 0 when they differ, used as the equality detector in comparator circuits (also called the coincidence or equivalence operator).

XOR (Exclusive OR) — A Boolean operation that outputs 1 when its two inputs differ and 0 when they are the same, serving as the fundamental building block for sum/difference computation in adders and subtractors, parity generation, and Gray code conversion.