References: Unit 7 — Multi-Level Gate Circuits

  1. NAND logic — Wikipedia — Comprehensive coverage of how NAND gates can implement all Boolean functions, including systematic conversion methods and practical circuit examples demonstrating universality.
  2. NOR logic — Wikipedia — Detailed explanation of NOR gate universality with implementation examples for basic gates and conversion techniques from standard logic forms to NOR-only circuits.
  3. Logic gate — Wikipedia — Overview of all logic gate types including standard symbols, truth tables, and transistor-level implementations in various technologies (TTL, CMOS, ECL).
  4. Digital Design (6th Edition) — M. Morris Mano, Michael D. Ciletti — Pearson — Chapter 3 covers multi-level gate circuits, NAND and NOR implementations, bubble pushing, and systematic conversion procedures with numerous worked examples.
  5. De Morgan's laws — Wikipedia — Foundation for the bubble pushing technique with proofs and applications in digital circuit design, gate conversion, and Boolean algebra simplification.
  6. NAND and NOR Implementation — GeeksforGeeks — Step-by-step tutorials on converting circuits to NAND-only and NOR-only implementations with worked examples covering both natural and cross conversions.
  7. Multi-Level Logic Optimization — TutorialsPoint — Coverage of factoring techniques, decomposition methods, and the trade-offs between circuit depth, gate count, and fan-in constraints.
  8. CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition) — Neil Weste, David Harris — Pearson — Chapters on logic design including AOI/OAI complex gates, technology mapping, gate loading effects, and CMOS circuit optimization techniques.
  9. Fan-out — Wikipedia — Explanation of fan-out constraints in digital circuits including effects on propagation delay, noise margins, and methods for increasing drive capability through buffer insertion.
  10. Technology mapping — Wikipedia — Overview of technology mapping in logic synthesis, covering decomposition into primitives, library cell matching, and covering algorithms used in ASIC design flows.