Glossary: Combinational Logic Modules

Key terms and definitions for Unit 8. Definitions follow ISO 11179 metadata registry standards.

A

Active-Low Output — A signal convention where the active or asserted state is represented by logic 0 (low voltage) rather than logic 1, often indicated by an overbar or bubble on a schematic symbol.

Adder Subtractor Circuit — A combinational circuit that performs both addition and subtraction operations using a control signal to select the operation mode.

ALU — Arithmetic Logic Unit, a combinational digital circuit that performs arithmetic operations such as addition and subtraction, and bitwise logical operations such as AND, OR, and XOR, based on a function-select input.

B

BCD Code — Binary-Coded Decimal, a representation where each decimal digit is encoded as a separate 4-bit binary number.

Binary to Gray Converter — A circuit that converts standard binary code to Gray code, where adjacent values differ by only one bit.

C

Code Converter — A combinational circuit that transforms data from one binary code format to another.

Combinational Logic — Digital circuits whose outputs depend only on current input values, not on previous states or history.

Comparator Circuit — A combinational circuit that compares two binary numbers and indicates their relative magnitude.

Control Signal — A digital signal that directs or modifies the operation of a circuit or system.

Critical Path — The longest signal propagation path from any input to the output in a logic circuit, which determines the circuit's maximum operating speed.

D

Decoder — A combinational circuit that converts an n-bit binary input code into 2^n output lines, activating exactly one output corresponding to the input value while all other outputs remain inactive.

Decoder Enable Input — A control signal on a decoder that, when inactive, forces all outputs to their inactive state regardless of the address inputs, enabling power reduction and cascaded expansion.

Decoder Tree Expansion — A hierarchical technique for building larger decoders from smaller ones by using the most significant address bits to generate enable signals that select which smaller decoder is active.

Demultiplexer — A combinational circuit that routes a single data input to one of 2^n outputs based on n select signals, with all non-selected outputs remaining at their inactive level.

E

Enable Signal — A control input that allows or prevents a circuit from operating or passing signals.

Encoder — A combinational circuit that converts a set of input lines, typically in one-hot format, into a compact binary code representing which input is active.

F

Full Adder — A combinational circuit that adds three input bits (two operands plus carry-in) producing a sum and carry-out.

Full Subtractor — A combinational circuit that subtracts one bit from another while accounting for a borrow input.

G

Gray Code — A binary code where successive values differ by exactly one bit, minimizing switching errors.

H

Half Adder — A combinational circuit that adds two single bits, producing a sum and carry output.

Half Subtractor — A combinational circuit that subtracts one bit from another, producing difference and borrow outputs.

M

Magnitude Comparator — A circuit that compares two multi-bit binary numbers and outputs their relative magnitude relationship.

Medium-Scale Integration — A classification of integrated circuits containing tens to hundreds of logic gates that implement functional building blocks such as multiplexers, decoders, encoders, and comparators.

Minterm Generation — The property of a decoder that produces all 2^n minterms of its n input variables on separate output lines, enabling implementation of any Boolean function by OR-ing selected outputs.

Multiplexer — A combinational circuit that selects one of 2^n data inputs and routes it to a single output, controlled by n select signals that determine which input is connected to the output.

Multiplexer Tree Expansion — A hierarchical construction technique that builds larger multiplexers from smaller ones by cascading levels, where lower-level MUXes handle the least significant select bits and upper-level MUXes handle the most significant bits.

O

One-Hot Encoding — A binary encoding scheme in which exactly one bit is high (1) at any time, with each bit position representing a unique state or input, commonly produced by decoders.

P

Priority Encoder — An encoder that accepts multiple simultaneously active inputs and produces the binary code of only the highest-priority active input, resolving ambiguity that a basic encoder cannot handle.

Propagation Delay — The time required for a signal change at a gate's input to produce a corresponding change at its output, measured from the input transition to the output reaching a valid logic level.

R

Ripple Carry Adder — An n-bit adder constructed by cascading full adders, where carry propagates through all stages.

S

Seven Segment Decoder — A combinational circuit that converts a binary or BCD input to the signals needed to display digits on a seven-segment display.

Seven Segment Display — An output device using seven LED or LCD segments arranged to display decimal digits 0-9.

Shannon Expansion — A theorem expressing a Boolean function as a sum of products involving a variable and its cofactors.

Sum Bit — The output bit in addition circuits that represents the sum of the input bits, excluding the carry.

T

Truth Table — A table listing all possible input combinations and corresponding output values for a logic function.

Two-Level Circuit — A logic circuit in which signals pass through at most two levels of gates from input to output, corresponding directly to sum-of-products (AND-OR) or product-of-sums (OR-AND) expressions.

V

Valid Flag — A single-bit output on a priority encoder that indicates whether any input is currently active, distinguishing between no active inputs and input zero being active.