Glossary: Sequential Logic Fundamentals

Key terms and definitions for Unit 9. Definitions follow ISO 11179 metadata registry standards.

A

Asynchronous Reset — A flip-flop control input that immediately forces the output to 0 regardless of the clock state, overriding normal clocked operation for initialization or emergency conditions.

Asynchronous Sequential Circuit — A sequential circuit in which state changes can occur at any time in response to input changes, without a synchronizing clock signal, making it faster but more susceptible to race conditions and hazards.

B

Bistable Element — A circuit with exactly two stable operating states, formed by cross-coupled inverters or gates with feedback, providing the fundamental physical mechanism for storing one bit of information.

C

Characteristic Table — A table that defines the next state of a flip-flop based on its current inputs and, for some types, the current state, describing the device's behavior from the perspective of "given inputs, find next state."

Clock Signal — A periodic square wave that alternates between logic 0 and logic 1, serving as the timing reference that synchronizes all state changes in a synchronous sequential circuit.

Clock-to-Q Delay — The time elapsed from the active clock edge until the flip-flop output Q settles to its new valid logic level, representing the flip-flop's output propagation delay.

D

D Flip-Flop — An edge-triggered memory element with a single data input D whose value is captured at the active clock edge and held at output Q until the next active edge, with the characteristic equation Q_next = D.

D Latch — A level-sensitive memory element that passes its data input D directly to output Q while the enable signal is active (transparent mode) and holds the last captured value when the enable goes inactive.

Duty Cycle — The percentage of a clock signal's period during which the signal is at logic high, expressed as the ratio of high time to total period.

E

Edge Detector — A small sequential circuit that produces a single-clock-cycle pulse when it detects a rising edge, falling edge, or both on an input signal, typically implemented using a flip-flop and combinational logic.

Edge-Triggered Device — A sequential circuit element that samples its inputs and updates its outputs only at the instant of a clock signal transition (rising or falling edge), ignoring input changes at all other times.

Excitation Table — The inverse of a characteristic table, showing the required flip-flop input values to produce a desired state transition from a known current state, essential for sequential circuit design.

F

Falling Edge — The transition of a digital signal from logic 1 (high) to logic 0 (low), used as the active clock edge in negative-edge-triggered sequential devices.

Feedback Loop — A signal path in which a circuit's output is routed back to one of its inputs, creating the ability to sustain a state and providing the fundamental mechanism for memory in sequential circuits.

G

Gated SR Latch — An SR latch augmented with an enable input that must be active for the set and reset inputs to affect the stored state, providing basic control over when state changes can occur.

H

Hold Time — The minimum duration that a flip-flop's data input must remain stable after the active clock edge to ensure the input value is correctly captured by the internal circuitry.

Hold Time Budgeting — The timing analysis practice of ensuring that data at a flip-flop's input remains stable for a sufficient duration after the active clock edge, accounting for minimum clock-to-output delays and routing variations.

J

JK Flip-Flop — An edge-triggered memory element with two inputs J and K that provides four operations: hold (J=K=0), reset (J=0, K=1), set (J=1, K=0), and toggle (J=K=1), with the characteristic equation Q_next = JQ' + K'Q.

L

Latch Inference — An unintended synthesis outcome where a level-sensitive latch is generated because a signal is not assigned a value on every possible execution path through a combinational process, creating implicit memory.

Level-Sensitive Device — A sequential circuit element whose output continuously tracks its data input whenever the enable or clock signal is at the active level, as opposed to sampling only at a clock edge.

M

Master-Slave Flip-Flop — A flip-flop constructed from two latches with complementary enables, where the master latch captures input data during one clock phase and the slave latch transfers it to the output during the opposite phase.

Metastability — An unstable condition in which a flip-flop's output voltage hovers between valid logic 0 and logic 1 levels for an unpredictable duration, caused by violating setup or hold time requirements.

P

Preset — An asynchronous flip-flop control input that immediately forces the output Q to logic 1, overriding normal clocked operation, typically active-low and used for initialization.

R

Race Condition — A circuit malfunction that occurs when the output of a latch or flip-flop feeds back through combinational logic to its own input and changes multiple times within a single clock period due to transparency.

Rising Edge — The transition of a digital signal from logic 0 (low) to logic 1 (high), used as the active clock edge in positive-edge-triggered sequential devices, which are the most common in modern designs.

S

Sequential Circuit — A digital circuit whose outputs depend on both current input values and the circuit's stored internal state, incorporating memory elements such as latches or flip-flops to retain information across time.

Sequential Logic — Digital circuits whose outputs depend on both current inputs and the history of past inputs.

Setup Time — The minimum duration that a flip-flop's data input must be stable before the active clock edge arrives to ensure the value is correctly captured and stored.

Setup Time Budgeting — The timing analysis practice of ensuring that data arrives and stabilizes at a flip-flop's input sufficiently before the active clock edge, accounting for clock period, combinational path delay, clock skew, and the flip-flop's setup requirement.

SR Latch — The most fundamental memory element, built from two cross-coupled NOR or NAND gates, with Set and Reset inputs that control the stored bit, and an invalid state when both inputs are simultaneously active.

State — The stored internal information of a sequential circuit at a given time, represented by the values held in its memory elements, which together with current inputs determines the circuit's outputs.

Synchronous Sequential Circuit — A sequential circuit in which all state changes are coordinated by a common clock signal, with memory elements updating only at defined clock edges, ensuring predictable and analyzable behavior.

T

T Flip-Flop — An edge-triggered memory element with a single toggle input T that either holds the current state (T = 0) or complements it (T = 1) at each active clock edge, with the characteristic equation Q_next = T XOR Q.

Timing Diagram — A graphical representation showing the values of multiple digital signals plotted against a common time axis, used to analyze and verify the temporal behavior of sequential circuits.

Transparency — The property of a level-sensitive latch in which the output continuously follows the input while the enable signal is active, allowing multiple input changes to propagate to the output within a single enable period.