End-of-Unit Problems: Sequential Logic Fundamentals

Work through these problems to reinforce your understanding of memory elements and sequential circuit timing.

Section A: Latches (5 problems)

Problem 1

Draw the circuit and complete the truth table for an SR latch using NOR gates.

Show Solution

NOR-based SR Latch circuit:

S ──────────┐
            ├──[NOR]───┬── Q'
   ┌────────┘          │
   │                   │
   │        ┌──────────┘
   │        │
   │        ├──[NOR]───┬── Q
   │        │          │
   │  R ────┘          │
   │                   │
   └───────────────────┘

Top NOR gate: inputs S and Q (feedback), output Q'
Bottom NOR gate: inputs Q' (feedback) and R, output Q
Cross-coupled: Q feeds back to top gate, Q' feeds back to bottom gate

Truth Table:

S	R	Q(next)	Q'(next)	State
0	0	Q	Q'	Hold (memory)
0	1	0	1	Reset
1	0	1	0	Set
1	1	0	0	Invalid (both low)

Characteristic equation:

Q(next) = S + R'Q

Invalid state: S = R = 1 causes Q = Q' = 0, which violates the complement relationship and causes race condition when both inputs return to 0.

Problem 2

Design an SR latch using NAND gates and compare its operation to the NOR-based version.

Show Solution

NAND-based SR Latch:

Note: Inputs are active-LOW (S̄ and R̄)

S' ─────────┐
            ├──[NAND]──┬── Q
   ┌────────┘          │
   │                   │
   │        ┌──────────┘
   │        │
   │        ├──[NAND]──┬── Q'
   │        │          │
   │  R' ───┘          │
   │                   │
   └───────────────────┘

Top NAND gate: inputs S̄ and Q' (feedback), output Q
Bottom NAND gate: inputs Q (feedback) and R̄, output Q'
Cross-coupled: Q feeds back to bottom gate, Q' feeds back to top gate

Truth Table (active-low inputs):

S̄	R̄	Q(next)	Q'(next)	State
0	0	1	1	Invalid
0	1	1	0	Set
1	0	0	1	Reset
1	1	Q	Q'	Hold

Comparison:

Feature	NOR Latch	NAND Latch
Active input level	HIGH (1)	LOW (0)
Set condition	S=1, R=0	S̄=0, R̄=1
Reset condition	S=0, R=1	S̄=1, R̄=0
Hold condition	S=0, R=0	S̄=1, R̄=1
Invalid condition	S=1, R=1	S̄=0, R̄=0

Problem 3

For the gated SR latch, draw the timing diagram for the following input sequence:

Initially: Q = 0
t=0 to t=2: EN=0, S=1, R=0
t=2 to t=4: EN=1, S=1, R=0
t=4 to t=6: EN=1, S=0, R=0
t=6 to t=8: EN=1, S=0, R=1
t=8 to t=10: EN=0, S=1, R=1

Show Solution

Gated SR Latch operation:

Q changes only when EN = 1

Analysis:

Time	EN	S	R	Q	Comment
0-2	0	1	0	0	Hold (EN=0)
2-4	1	1	0	1	Set (Q→1)
4-6	1	0	0	1	Hold
6-8	1	0	1	0	Reset (Q→0)
8-10	0	1	1	0	Hold (EN=0)

Timing Diagram:

      0         2         4         6         8        10
      |         |         |         |         |         |

EN   ___________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________

S    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_____________________________|‾‾‾‾‾‾‾‾‾‾

R    _____________________________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

Q    ___________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_____________________________|

Problem 4

Design a D latch using an SR latch and additional gates. Explain why the D latch eliminates the invalid state problem.

Show Solution

D Latch from SR Latch:

        ┌────────────────[AND]──── S ──┐
        │                  │           │
D ──────┤     EN ──────────┤           ├──[SR Latch]── Q, Q'
        │                  │           │
        └──[NOT]─────────[AND]──── R ──┘

Equations:

S = D · EN
R = D' · EN

Why invalid state is eliminated:

When EN = 0:

S = D · 0 = 0
R = D' · 0 = 0
Latch holds (valid)

When EN = 1:

If D = 1: S = 1, R = 0 (Set - valid)
If D = 0: S = 0, R = 1 (Reset - valid)

Key insight: S and R can never both be 1 simultaneously because:

S = D · EN
R = D' · EN
S · R = D · EN · D' · EN = 0 (since D · D' = 0)

Truth Table:

EN	D	S	R	Q(next)
0	X	0	0	Q (hold)
1	0	0	1	0
1	1	1	0	1

Characteristic equation: Q(next) = D when EN=1, else Q(hold)

Problem 5

What is the difference between a latch and a flip-flop? Give an example timing scenario where this difference matters.

Show Solution

Fundamental Difference:

Property	Latch	Flip-Flop
Trigger	Level-sensitive	Edge-triggered
Response	Changes while enable HIGH	Changes only at clock edge
Transparency	Transparent when enabled	Never transparent

Level-sensitive (Latch):

Output follows input continuously while enabled
Called "transparent" latch

Edge-triggered (Flip-Flop):

Output changes only at rising or falling clock edge
Input sampled at edge moment, ignored otherwise

Example where difference matters:

Circuit: D-type element with feedback: Q connected to D through inverter

    ┌──[NOT]─────────────────────┐
    │                            │
    └───── D ──[D Element]── Q ──┴── Output
                    │
    CLK ────────────┘

With D Latch (EN = CLK):

When CLK HIGH: Q changes, then D' (inverted) feeds back
Q oscillates rapidly while CLK is HIGH
Creates unpredictable, unstable behavior

With D Flip-Flop:

Q changes only at clock edge
New Q value doesn't affect input until next edge
Output toggles cleanly once per clock cycle
Creates a divide-by-2 frequency divider

Conclusion: Flip-flops are essential for synchronous sequential circuits where feedback exists, as they prevent transparency-caused oscillations.

Section B: Flip-Flops (6 problems)

Problem 6

Complete the characteristic table and excitation table for a D flip-flop.

Show Solution

D Flip-Flop Characteristic Table:

(What Q becomes for each D input)

D	Q(next)
0	0
1	1

Characteristic equation: Q(next) = D

D Flip-Flop Excitation Table:

(What D must be to achieve desired transition)

Q	Q(next)	D required
0	0	0
0	1	1
1	0	0
1	1	1

Pattern: D = Q(next) always

Simplification: D equals whatever you want Q to become.

This makes D flip-flops the easiest to use in design!

Problem 7

Complete the characteristic table and excitation table for a JK flip-flop.

Show Solution

JK Flip-Flop Characteristic Table:

J	K	Q(next)	Operation
0	0	Q	Hold
0	1	0	Reset
1	0	1	Set
1	1	Q'	Toggle

Characteristic equation: Q(next) = JQ' + K'Q

JK Flip-Flop Excitation Table:

Q	Q(next)	J	K
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

How to read:

Q: 0→0: J must be 0 (don't set), K can be anything
Q: 0→1: J must be 1 (set), K can be anything
Q: 1→0: J can be anything, K must be 1 (reset)
Q: 1→1: J can be anything, K must be 0 (don't reset)

Problem 8

Complete the characteristic table and excitation table for a T flip-flop.

Show Solution

T Flip-Flop Characteristic Table:

T	Q(next)	Operation
0	Q	Hold
1	Q'	Toggle

Characteristic equation: Q(next) = T ⊕ Q = TQ' + T'Q

T Flip-Flop Excitation Table:

Q	Q(next)	T required
0	0	0 (hold)
0	1	1 (toggle)
1	0	1 (toggle)
1	1	0 (hold)

Pattern: T = Q ⊕ Q(next)

T = 1 when Q needs to change, T = 0 when Q stays same.

T from JK: A JK flip-flop with J = K = T becomes a T flip-flop.

Problem 9

Draw the timing diagram for a positive-edge-triggered D flip-flop with the following inputs:

Clock: Square wave with period 4 time units D: 0 from t=0-3, 1 from t=3-7, 0 from t=7-10

Initial Q = 0

Show Solution

Clock edges at: t = 2, 4, 6, 8, 10, ... (rising edges)

Analysis at each rising edge:

Time	D at edge	Q after edge
t=2	D=0	Q=0
t=4	D=1	Q=1
t=6	D=1	Q=1
t=8	D=0	Q=0

Timing Diagram:

      0     1     2     3     4     5     6     7     8     9    10
      |     |     |     |     |     |     |     |     |     |     |

CLK  _|‾‾‾‾‾|_____|‾‾‾‾‾|_____|‾‾‾‾‾|_____|‾‾‾‾‾|_____|‾‾‾‾‾|_____

D    ______________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|________________________

Q    ________________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|______________

Key observations:

Q changes only at rising clock edges (t=2,4,6,8,...)
D value is sampled at edge moment
At t=2: D=0, so Q stays 0
At t=4: D=1 (changed at t=3), so Q→1
At t=8: D=0 (changed at t=7), so Q→0

Problem 10

Convert a D flip-flop to a T flip-flop using external logic.

Show Solution

T flip-flop behavior:

T=0: Q holds
T=1: Q toggles

D flip-flop behavior:

D=0: Q→0
D=1: Q→1

Required relationship:

When T=0: D should equal Q (hold)
When T=1: D should equal Q' (toggle)

Logic equation:

D = T'Q + TQ' = T ⊕ Q

Circuit:

T ──────┐
        ├──[XOR]── D ──[D FF]──┬── Q
   ┌────┘               │      │
   │           CLK ──────┘      │
   │                            │
   └────────────────────────────┘

Components needed:

1 D flip-flop
1 XOR gate

Verification:

T	Q	D=T⊕Q	Q(next)
0	0	0	0 (hold)
0	1	1	1 (hold)
1	0	1	1 (toggle)
1	1	0	0 (toggle)

✓ Matches T flip-flop behavior

Problem 11

A JK flip-flop has the following input sequence. Determine Q after each clock pulse.

Initial Q = 0 - Pulse 1: J=1, K=0 - Pulse 2: J=1, K=1 - Pulse 3: J=0, K=1 - Pulse 4: J=1, K=1 - Pulse 5: J=0, K=0

Show Solution

JK Flip-Flop operation:

J=0, K=0: Hold
J=0, K=1: Reset (Q→0)
J=1, K=0: Set (Q→1)
J=1, K=1: Toggle (Q→Q')

Step-by-step analysis:

Pulse	J	K	Q(before)	Operation	Q(after)
Initial	-	-	-	-	0
1	1	0	0	Set	1
2	1	1	1	Toggle	0
3	0	1	0	Reset	0
4	1	1	0	Toggle	1
5	0	0	1	Hold	1

Final Q = 1

Section C: Timing Parameters (4 problems)

Problem 12

A D flip-flop has the following timing parameters:

Setup time (tsu): 2 ns
Hold time (th): 1 ns
Clock-to-Q delay (tCQ): 3 ns

If the clock period is 10 ns, what is the maximum combinational logic delay allowed between two flip-flops?

Show Solution

Timing constraint equation:

tCQ + tlogic + tsu ≤ Tclk

Where:

tCQ = Clock-to-Q delay of source FF
tlogic = Combinational logic delay
tsu = Setup time of destination FF
Tclk = Clock period

Solving for maximum tlogic:

tlogic ≤ Tclk - tCQ - tsu tlogic ≤ 10 - 3 - 2 tlogic ≤ 5 ns

Diagram:

Clock edge --> [tCQ: 3ns] --> Q changes --> [tlogic: <=5ns] -->
D arrives --> [tsu: 2ns] --> Next clock edge

Total: 3 + 5 + 2 = 10 ns = Tclk

Hold time check:

The new D input must not change too quickly after clock edge. This is usually satisfied by tCQ > th (3 ns > 1 ns ✓)

Problem 13

Explain what happens when setup time is violated. What is metastability?

Show Solution

Setup Time Violation:

Setup time violation occurs when the D input changes too close to (within tsu of) the clock edge.

Consequences:

The flip-flop may capture the old value
The flip-flop may capture the new value
The flip-flop may enter a metastable state

Metastability:

Metastability is an unstable intermediate state between logic 0 and logic 1.

Characteristics of metastable state:

Property	Normal Operation	Metastable
Output voltage	VOL or VOH	Between VOL and VOH
Duration	tCQ (predictable)	Unpredictable
Final state	Deterministic	Random

Why it happens:

The flip-flop's internal feedback loop needs time to resolve
When input changes at the sampling moment, the loop has insufficient energy to reach a stable state quickly
Eventually resolves to 0 or 1, but timing is unpredictable

Problems caused:

Output may be in "forbidden zone" for downstream logic
Different fanout gates may interpret it differently (some as 0, some as 1)
Timing becomes unpredictable
Can cause system crashes or data corruption

Mitigation:

Use synchronizer chains (two flip-flops in series)
Design with sufficient timing margin
Use faster flip-flops with better metastability characteristics

Problem 14

Two flip-flops are connected with combinational logic between them. Calculate the minimum clock period if:

FF1: tCQ = 2 ns
FF2: tsu = 3 ns, th = 1 ns
Logic delay: 4 ns (typical), 6 ns (maximum)
Clock skew: 0.5 ns

Show Solution

Setup time constraint (using maximum logic delay):

Tclk ≥ tCQ + tlogic(max) + tsu + tskew

Tclk ≥ 2 + 6 + 3 + 0.5 Tclk ≥ 11.5 ns

Maximum clock frequency:

fmax = 1 / Tclk = 1 / 11.5 ns ≈ 87 MHz

Hold time constraint:

tCQ + tlogic(min) ≥ th + tskew

Assuming tlogic(min) ≈ 0 (worst case for hold):

2 + 0 ≥ 1 + 0.5 2 ≥ 1.5 ✓

Hold time is satisfied.

Timing diagram:

FF1 CLK edge --> [tCQ=2ns] --> Q1 valid -->
[tlogic=6ns max] --> D2 valid -->
[tsu=3ns before FF2 CLK] --> FF2 CLK edge

With skew: FF2 CLK can be up to 0.5ns early

Problem 15

A master-slave flip-flop has an inherent timing issue called "ones catching" or "zeros catching." Explain this problem and how edge-triggered flip-flops solve it.

Show Solution

Master-Slave Flip-Flop Structure:

D ──── [Master Latch] ──── [Slave Latch] ──── Q
         (CLK=1 active)      (CLK=0 active)

Operation:

CLK = 1: Master transparent, slave holds
CLK = 0: Master holds, slave transparent

"Ones Catching" Problem:

During CLK = 1 phase, the master latch is transparent.

If D has a momentary glitch to 1 (noise, switching transient):

D    ________________|‾‾‾|____________________  (brief spike)

CLK  ___________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|________  (master active during spike)

The master captures the glitch (stores 1), even though D returns to 0 before the clock edge. When CLK falls, this erroneous 1 transfers to the slave.

"Zeros Catching":

Similarly, if master stores 1 and D momentarily glitches to 0 while CLK=1, the master captures the unwanted 0.

Edge-Triggered Solution:

True edge-triggered flip-flops sample D only at the precise clock edge moment:

                  ↓ (only this instant matters)
CLK  _____________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|________________

Implementation differences:

Type	Sampling Window	Susceptibility
Master-Slave	Entire CLK=1 period	High (glitch-sensitive)
Edge-triggered	~0 ns at edge	Low (edge only)

Modern practice: Use true edge-triggered flip-flops (typically implemented with transmission gates and feedback) to avoid this issue.

Section D: Timing Diagram Analysis (3 problems)

Problem 16

Given the following timing diagram, determine what type of flip-flop is being used and explain your reasoning.

CLK  _|‾|_|‾|_|‾|_|‾|_|‾|_
     0   2   4   6   8   10

D    __|‾‾‾‾|___|‾‾‾|____
       1    4   6   9

Q    ____|‾‾‾|_____|‾‾|__
         2    6    8

Show Solution

Analysis of transitions:

Clock Edge	D Value	Q Transition
t=2 (↑)	1	0→1
t=4 (↑)	0	1→1 (no change until...)
t=6 (↑)	0	1→0
t=8 (↑)	1	0→1

Wait, let me re-examine...

At t=2: D is 1, Q goes to 1 ✓ At t=4: D is 0, but Q stays 1? Let me re-read the diagram.

Actually looking at Q: changes at t=2, t=6, t=8

At t=2: D=1, Q: 0→1 (follows D) ✓ At t=4: D=0, Q stays 1 (doesn't follow immediately) At t=6: D=0 (since t=4), Q: 1→0 (follows D) At t=8: D=1 (since t=6), Q: 0→1 (follows D)

Conclusion:

Q changes only at rising clock edges, and Q follows whatever D is at that edge.

This is a positive-edge-triggered D flip-flop

Verification:

At t=2: D=1 → Q=1 ✓
At t=4: D=0 → Q should be 0...but diagram shows Q=1

Let me re-check the diagram. Q goes high at t=2, stays high until t=6.

This means at t=4 edge, D was actually still 1 (D went low at exactly t=4, after the edge).

Confirmed: Positive-edge-triggered D flip-flop

Problem 17

Draw the timing diagram for a JK flip-flop (positive-edge-triggered) with:

Initial Q = 0
J: 1 from t=0-6, 0 from t=6-12
K: 0 from t=0-4, 1 from t=4-12
Clock period: 2 (edges at t=1, 3, 5, 7, 9, 11)

Show Solution

Clock rising edges at: t = 1, 3, 5, 7, 9, 11

Analysis at each edge:

Edge	J	K	Q(before)	Q(after)	Operation
t=1	1	0	0	1	Set
t=3	1	0	1	1	Set (hold)
t=5	1	1	1	0	Toggle
t=7	0	1	0	0	Reset (hold)
t=9	0	1	0	0	Reset (hold)
t=11	0	1	0	0	Reset (hold)

Timing Diagram:

     0    1    2    3    4    5    6    7    8    9   10   11   12
     |    |    |    |    |    |    |    |    |    |    |    |    |

CLK  _|‾‾‾|____|‾‾‾|____|‾‾‾|____|‾‾‾|____|‾‾‾|____|‾‾‾|____|‾‾‾|____

J    ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_____________________________________

K    _____________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

Q    _____|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|___________________________________________

Problem 18

Given a T flip-flop with asynchronous PRESET and CLEAR inputs (both active-low), draw the timing diagram for:

Initial Q = 0
T: Always 1
PRESET: Low from t=0-1 only
CLEAR: Low from t=5-6 only
Clock edges at t=2, 3, 4, 7, 8

Show Solution

Asynchronous inputs override clock:

PRESET low → Q = 1 immediately
CLEAR low → Q = 0 immediately

T=1 means toggle at each clock edge

Analysis:

Time	Event	Q
t=0	Initial	0
t=0-1	PRESET low	1 (async set)
t=2	CLK edge, T=1	0 (toggle)
t=3	CLK edge, T=1	1 (toggle)
t=4	CLK edge, T=1	0 (toggle)
t=5-6	CLEAR low	0 (async clear)
t=7	CLK edge, T=1	1 (toggle)
t=8	CLK edge, T=1	0 (toggle)

Timing Diagram:

        0       1       2       3       4       5       6       7       8       9
        |       |       |       |       |       |       |       |       |       |

CLK    _________________|‾‾‾|___|‾‾‾|___|‾‾‾|_________________|‾‾‾|___|‾‾‾|_______

T      ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

PRESET |_______|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

CLEAR  ‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾

Q      __|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|_______|‾‾‾‾‾‾‾|_________________________|‾‾‾‾‾‾‾|____

Section E: Sequential Circuit Analysis (2 problems)

Problem 19

Analyze the following circuit. Determine its function.

         ┌──────────────────────────────────┐
         │                                  │
         └─── D ──[D FF]──── Q ──── Output  │
                    │                       │
         CLK ──────┘    Q' ────────────────┘

Show Solution

Circuit Analysis:

D input is connected to Q' (complement of output)

At each clock edge:

D = Q' (previous Q inverted) Q(next) = D = Q'(previous)

This is a T flip-flop with T=1 (toggle mode)

Behavior:

Clock	Q(before)	D = Q'	Q(after)
1	0	1	1
2	1	0	0
3	0	1	1
4	1	0	0

Function: Divide-by-2 (Frequency Divider)

Output frequency = Input clock frequency / 2

Timing:

CLK  _|‾‾‾|____|‾‾‾|____|‾‾‾|____|‾‾‾|____|‾‾‾|____|‾‾‾|____|‾‾‾|____|‾‾‾|____

Q    ________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|________________|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|________________

Q completes one cycle for every two clock cycles.

Problem 20

Determine the state sequence for the following circuit:

Two D flip-flops: FF0 (Q₀) and FF1 (Q₁)
- Both share the same clock
- D₀ = Q₁
- D₁ = Q₀ ⊕ Q₁

Initial state: Q₁Q₀ = 00

Show Solution

State Transition Analysis:

Next state equations:

Q₀(next) = D₀ = Q₁
Q₁(next) = D₁ = Q₀ ⊕ Q₁

State sequence:

Clock	Q₁	Q₀	D₁=Q₀⊕Q₁	D₀=Q₁	Next Q₁Q₀
0	0	0	0	0	00
1	0	0	0	0	00

Wait, this shows it stays at 00. Let me check if initial state should be different.

Let's try starting from 01:

Clock	Q₁	Q₀	D₁=Q₀⊕Q₁	D₀=Q₁	Next Q₁Q₀
-	0	1	1	0	10
1	1	0	1	1	11
2	1	1	0	1	01
3	0	1	1	0	10
...	(cycle repeats)

State diagram:

01 --> 10 --> 11 --> 01 (cycle of 3 states)

00 --> 00 (stuck state)

This is a mod-3 counter (excluding 00 state)

If starting from 00, circuit stays at 00. If starting from any other state, cycles through: 01 → 10 → 11 → 01...

Sequence from 00: 00 → 00 → 00 (stuck) Sequence from 01: 01 → 10 → 11 → 01 → 10 → 11 → ...

Summary

Section	Topics Covered	Problem Count
A	Latches	5
B	Flip-Flops	6
C	Timing Parameters	4
D	Timing Diagrams	3
E	Circuit Analysis	2
Total		20