Skip to content

CLB Architecture

Description

This simulation shows the internal architecture of a Configurable Logic Block (CLB) found in modern FPGAs. It includes two 4-input LUTs, two flip-flops, multiplexers, and a carry chain, demonstrating how these elements work together.

Learning Objectives

Bloom Level: Analyze (L4)

  • Identify the components within a CLB
  • Trace signal paths through LUTs, MUXes, and flip-flops
  • Understand the role of the carry chain for arithmetic
  • Analyze how CLB configuration bits control routing

How to Use

  1. Click on LUT, FF, MUX, or Carry components to select them
  2. View detailed information about the selected component
  3. Toggle the bypass MUX to route LUT output directly or through the flip-flop
  4. Observe signal flow highlighted through the CLB

References

  • Unit 11: Programmable Logic Devices - FPGA CLB Architecture