MicroSims
Interactive educational simulations for learning digital system design.
Course Overview
| MicroSim | Bloom Level | Description |
|---|---|---|
| Course Structure Tree | L2 Understand | Interactive tree diagram of the textbook hierarchy |
Unit 1: Number Systems
| MicroSim | Bloom Level | Description |
|---|---|---|
| Base Converter | L3 Apply | Convert between binary, decimal, octal, hexadecimal |
| Analog vs Digital Signals | L2 Understand | Compare analog and digital signal characteristics |
| Positional Notation Explorer | L2 Understand | Explore place values in different number bases |
| Binary Arithmetic Practice | L3 Apply | Practice binary addition and subtraction |
| Signed Number Comparison | L4 Analyze | Compare sign-magnitude, 1's and 2's complement |
| Overflow Detection Simulator | L4 Analyze | Detect overflow in signed arithmetic |
| Number Systems Concept Map | L2 Understand | Interactive concept map of number systems |
| Base Conversion Walkthrough | L3 Apply | Step-by-step base conversion with multi-base input |
Unit 2: Boolean Algebra
| MicroSim | Bloom Level | Description |
|---|---|---|
| AND Gate Truth Table | L2 Understand | Interactive AND gate with truth table |
| OR Gate Truth Table | L2 Understand | Interactive OR gate with truth table |
| NOT Gate Truth Table | L2 Understand | Interactive NOT gate with truth table |
| Buffer Gate Truth Table | L2 Understand | Interactive buffer gate with truth table |
| Tri-State Buffer Truth Table | L2 Understand | Interactive tri-state buffer with truth table |
| NAND Gate Truth Table | L2 Understand | Interactive NAND gate with truth table |
| NOR Gate Truth Table | L2 Understand | Interactive NOR gate with truth table |
| XOR Gate Truth Table | L2 Understand | Interactive XOR gate with truth table |
| XNOR Gate Truth Table | L2 Understand | Interactive XNOR gate with truth table |
| Logic Gate Simulator | L4 Analyze | Interactive AND, OR, NOT, NAND, NOR, XOR, XNOR gates |
| Boolean Operations Visualizer | L2 Understand | Visualize Boolean operations with Venn diagrams |
| Truth Table Generator | L3 Apply | Generate truth tables for Boolean expressions |
| Boolean Laws Explorer | L2 Understand | Explore Boolean algebra laws interactively |
| De Morgan's Theorem Visualizer | L4 Analyze | Visualize De Morgan's theorem transformations |
| Boolean Simplification Tutor | L3 Apply | Step-by-step Boolean expression simplification |
| 3-Input AND Gate | L2 Understand | Interactive 3-input AND gate with truth table |
| 3-Input OR Gate | L2 Understand | Interactive 3-input OR gate with truth table |
| 3-Input NAND Gate | L2 Understand | Interactive 3-input NAND gate with truth table |
| 3-Input NOR Gate | L2 Understand | Interactive 3-input NOR gate with truth table |
| 3-Input XOR Gate | L2 Understand | Interactive 3-input XOR gate with truth table |
| Gate Cascade Simulator | L4 Analyze | Simulate multi-level logic gate circuits |
| Circuit Analysis & Synthesis | L5 Evaluate | Analyze and synthesize logic circuits |
| Boolean Proof Walkthrough | L3 Apply | Step-by-step Boolean algebra proof walkthrough |
Unit 3: Applications of Boolean Algebra
| MicroSim | Bloom Level | Description |
|---|---|---|
| Binary Adder Visualizer | L2 Understand | Step through half adder and full adder operations |
| Design Flow Visualization | L2 Understand | Visualize the digital design flow |
| Word Problem Translator | L3 Apply | Translate word problems to Boolean expressions |
| Adder-Subtractor Builder | L6 Create | Build and understand adder-subtractor circuits |
| Parity Circuit Simulator | L3 Apply | Simulate parity generation and checking |
| Code Converter Demo | L3 Apply | Convert between Binary, Gray, BCD, Excess-3 |
| Seven Segment Decoder | L3 Apply | Design and test a 7-segment decoder |
| Don't Care Optimizer | L4 Analyze | Show how don't cares enable optimization |
| Full Adder Walkthrough | L3 Apply | Step-by-step full adder design walkthrough |
Unit 4: Minterm & Maxterm Expansions
| MicroSim | Bloom Level | Description |
|---|---|---|
| Minterm/Maxterm Converter | L3 Apply | Convert between SOP and POS canonical forms |
| Minterm Visualizer | L2 Understand | Visualize minterms and maxterms |
| SOP-POS Converter | L3 Apply | Convert between SOP and POS forms |
| Shannon Expansion Explorer | L4 Analyze | Explore Shannon's expansion theorem |
| Minterm Expansion Walkthrough | L3 Apply | Step-by-step minterm expansion walkthrough |
| Truth Table Canonical Form | L3 Apply | Click truth table outputs to generate canonical SOP and POS expressions |
Unit 5: Karnaugh Maps
| MicroSim | Bloom Level | Description |
|---|---|---|
| K-Map Solver | L4 Analyze | Interactive 2-4 variable K-map simplification |
| K-Map 3-Variable Simulator | L3 Apply | Interactive 3-variable K-map |
| Prime Implicant Finder | L4 Analyze | Find prime and essential prime implicants |
| K-Map with Don't Cares | L3 Apply | K-map simplification with don't cares |
| K-Map Practice Challenge | L3 Apply | Practice problems for K-map simplification |
| K-Map Simplification Walkthrough | L3 Apply | Step-by-step K-map simplification walkthrough |
Unit 6: Quine-McCluskey Method
| MicroSim | Bloom Level | Description |
|---|---|---|
| QM Grouping Visualization | L2 Understand | Classify minterms by 1-count |
| QM Combination Simulator | L3 Apply | Step-through combination process |
| PI Chart Interactive | L4 Analyze | Find essential PIs and minimum cover |
| QM Complexity Chart | L5 Evaluate | Compare exact vs heuristic methods |
| QM Complete Walkthrough | L6 Create | Full end-to-end QM solver |
| QM Method Walkthrough | L3 Apply | Step-by-step Quine-McCluskey method walkthrough |
Unit 7: Multi-Level Gate Circuits
| MicroSim | Bloom Level | Description |
|---|---|---|
| Universal Gate Simulator | L2-L3 Apply | NAND/NOR implementing any gate |
| Bubble Pushing Simulator | L4 Analyze | Interactive bubble pushing technique |
| NAND-NOR Converter | L3-L4 Apply | Convert between NAND/NOR implementations |
| Multi-Level Analyzer | L4-L5 Evaluate | Analyze propagation delay and critical path |
| NAND Conversion Walkthrough | L3 Apply | Step-by-step NAND gate conversion walkthrough |
| Critical Path Delay Explorer | L4 Analyze | Visualize propagation delay and critical path through multi-level gate circuits |
Unit 8: Combinational Logic Modules
| MicroSim | Bloom Level | Description |
|---|---|---|
| MUX Simulator | L2-L3 Apply | Interactive 4-to-1 multiplexer |
| Decoder Simulator | L2-L3 Apply | Interactive 2-to-4 decoder |
| Priority Encoder Simulator | L2-L3 Apply | 4-to-2 priority encoder |
| Binary-Gray Converter | L2-L3 Apply | Convert between Binary and Gray code |
| Magnitude Comparator | L2-L3 Apply | 4-bit magnitude comparator |
| MUX Function Walkthrough | L3 Apply | Step-by-step MUX function implementation walkthrough |
Unit 9: Sequential Logic Fundamentals
| MicroSim | Bloom Level | Description |
|---|---|---|
| SR Latch Simulator | L2-L4 Analyze | Interactive NOR-gate SR latch |
| D Flip-Flop Simulator | L2-L3 Apply | Edge-triggered D flip-flop |
| JK Flip-Flop Simulator | L2-L3 Apply | JK flip-flop with toggle |
| Timing Diagram Analyzer | L3-L4 Analyze | Analyze flip-flop timing diagrams |
| Flip-Flop Timing Walkthrough | L3 Apply | Step-by-step flip-flop timing analysis walkthrough |
| Setup & Hold Time Explorer | L4 Analyze | Interactive setup time, hold time, and metastability visualization |
Unit 10: Sequential Circuit Design
| MicroSim | Bloom Level | Description |
|---|---|---|
| Shift Register Simulator | L2-L3 Apply | 4-bit shift register |
| Counter Simulator | L2-L3 Apply | 4-bit binary up/down counter |
| FSM Designer | L2-L4 Analyze | Moore state machine simulator |
| Sequence Detector Demo | L3-L4 Analyze | "101" pattern detector |
| Shift Register Walkthrough | L3 Apply | Step-by-step shift register design walkthrough |
| Moore vs Mealy Comparison | L4 Analyze | Side-by-side Moore and Mealy state machine comparison |
Unit 11: Programmable Logic Devices
| MicroSim | Bloom Level | Description |
|---|---|---|
| Programmable Connections | L2 Understand | Compare fuse, antifuse, SRAM, and flash connection technologies |
| ROM Architecture | L2 Understand | ROM structure with address decoder and OR-plane output array |
| PLA Architecture | L3 Apply | Interactive PLA with programmable AND and OR arrays |
| PLA vs PAL Comparison | L4 Analyze | Side-by-side comparison of PLA and PAL architectures |
| CPLD Architecture | L2 Understand | CPLD block diagram with function blocks and interconnect matrix |
| LUT Explorer | L3 Apply | 4-input lookup table implementing any Boolean function |
| CLB Architecture | L4 Analyze | FPGA Configurable Logic Block internal architecture |
| FPGA Configuration Flow | L2 Understand | Compare SRAM-based and flash-based FPGA configuration |
| FPGA Design Flow | L1 Remember | Complete 10-step FPGA design flow with feedback loops |
| PLD Selection Tree | L5 Evaluate | Interactive decision tree for PLD selection |
| PLA Programming Walkthrough | L3 Apply | Step-by-step PLA programming walkthrough |
Unit 12: VHDL
| MicroSim | Bloom Level | Description |
|---|---|---|
| Entity-Architecture Explorer | L2 Understand | Visualize VHDL entity declarations and architecture bodies |
| VHDL Modeling Styles | L4 Analyze | Compare dataflow, structural, and behavioral modeling |
| VHDL Flip-Flop Patterns | L3 Apply | DFF variant VHDL patterns with timing diagrams |
| VHDL FSM Mapper | L4 Analyze | Cross-highlight between VHDL FSM code and state diagram |
| VHDL Synthesis Inference | L2 Understand | Code patterns mapped to inferred hardware |
| VHDL FSM Walkthrough | L3 Apply | Step-by-step VHDL FSM design walkthrough |
Unit 13: System Integration
| MicroSim | Bloom Level | Description |
|---|---|---|
| Top-Down Design Flow | L2 Understand | 6-step top-down design methodology with verification feedback |
| Datapath-Controller Interaction | L4 Analyze | Interactive datapath with FSM controller and clock stepping |
| Timing Analysis Visualizer | L3 Apply | Critical path delays and maximum clock frequency calculation |
| Digital Lock System | L6 Create | Complete digital lock with keypad, FSM, and lockout |
| UART Transmitter | L3 Apply | UART serial transmission with shift register and waveform |
| Course Integration Map | L5 Evaluate | Force-directed graph of all 13 course units |
| Datapath-Controller Walkthrough | L3 Apply | Step-by-step datapath-controller design walkthrough |
| UART Transceiver | L4 Analyze | RTL block diagram of UART transceiver with controller-datapath separation and 16x oversampling |
| Vending Machine FSM | L4 Analyze | Controller-datapath vending machine with accumulator balance register and 5-state Moore FSM |
| Hierarchical ALU Design | L4 Analyze | Interactive tree showing hierarchical decomposition of an 8-bit calculator |
Summary Statistics
| Unit | Count | Bloom Levels |
|---|---|---|
| Course Overview | 1 | L2 |
| Unit 1: Number Systems | 8 | L2-L4 |
| Unit 2: Boolean Algebra | 23 | L2-L5 |
| Unit 3: Applications | 9 | L2-L6 |
| Unit 4: Minterms/Maxterms | 6 | L2-L4 |
| Unit 5: Karnaugh Maps | 6 | L3-L4 |
| Unit 6: Quine-McCluskey | 6 | L2-L6 |
| Unit 7: Multi-Level Gates | 6 | L2-L5 |
| Unit 8: Combinational Modules | 6 | L2-L3 |
| Unit 9: Sequential Fundamentals | 6 | L2-L4 |
| Unit 10: Sequential Design | 6 | L2-L4 |
| Unit 11: Programmable Logic | 11 | L1-L5 |
| Unit 12: VHDL | 6 | L2-L4 |
| Unit 13: System Integration | 10 | L2-L6 |
| Total | 110 | L1-L6 |
About MicroSims
MicroSims are lightweight, interactive educational simulations designed for browser-based learning. They feature:
- Responsive Design: Adapt to any screen width
- Immediate Feedback: See results of parameter changes instantly
- Focused Scope: Each addresses a specific learning objective
- Accessibility: Screen reader support and keyboard navigation
Using MicroSims
MicroSims can be:
- Viewed inline in textbook chapters via iframe embedding
- Opened fullscreen using the "View Fullscreen" button
- Embedded in other websites using the provided iframe code