Critical Path Delay Explorer

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Description

Explore how signal propagation delay accumulates through a multi-level combinational circuit. This MicroSim visualizes a 3-level gate network with NOT, AND, and OR gates. Each gate has a configurable delay, and the simulator computes all input-to-output paths, highlights the critical path (longest total delay) in red, and displays a detailed breakdown of every path's delay. Adjust individual gate delays to see how the critical path shifts in real time.

Learning Objectives

Bloom Level: Analyze (L4)

After using this MicroSim, students will be able to:

  • ✓ Identify the critical path in a multi-level gate circuit
  • ✓ Calculate total propagation delay along each input-to-output path
  • ✓ Understand how gate delays combine in series through multiple logic levels
  • ✓ Predict how changing a single gate delay affects which path becomes critical

How to Use

  1. Observe the 3-level gate circuit diagram with inputs A, B, C, D flowing through gates to output F
  2. Identify the critical path highlighted in red — this is the longest delay path from any input to the output
  3. Read the path delay analysis table to see the delay breakdown for all five input-to-output paths
  4. Adjust individual gate delays using the +/− buttons in the control area at the bottom
  5. Experiment to find delay settings that shift the critical path from one route to another

Circuit Topology

The circuit implements F = (A' + B·C) · (C·D) using five gates across three levels:

  • Level 1: G1 = NOT(A), G2 = AND(B, C)
  • Level 2: G3 = OR(G1, G2), G4 = AND(C, D)
  • Level 3: G5 = AND(G3, G4) → Output F

References