NAND-NOR Converter

← Back to Unit 7

Description

This MicroSim converts Boolean expressions between three different gate-level implementations: AND-OR (standard two-level), NAND-only, and NOR-only. Converting between these representations is a fundamental skill in digital design, as real-world circuits are often implemented using only NAND gates (in CMOS technology) for manufacturing efficiency.

Key Features

  • ● Selectable Boolean expressions of varying complexity
  • ● Side-by-side AND-OR, NAND-only, and NOR-only circuit displays
  • ● Visual representation of gate-level implementations
  • ● Gate count comparison across all three implementations
  • ● Clear demonstration of the double-inversion conversion technique

Learning Objectives

Bloom Level: Apply (L3)

After using this MicroSim, students will be able to:

  • ✓ Convert a two-level AND-OR expression into an equivalent NAND-only implementation
  • ✓ Convert a two-level OR-AND expression into an equivalent NOR-only implementation
  • ✓ Compare gate counts across implementations and explain why NAND is preferred in CMOS design

How to Use

  1. Select a Boolean expression from the dropdown (e.g., AB + CD, A'B + AB')
  2. View the AND-OR implementation showing the standard two-level circuit
  3. Observe the NAND-only and NOR-only implementations
  4. Compare the gate counts between the three implementations
  5. Try different expressions to see how circuit complexity varies
  6. Trace through each circuit mentally to verify equivalence

Lesson Plan

Before the Simulation (5 minutes)

  • Review DeMorgan's theorem: (AB)' = A' + B' and (A+B)' = A'B'
  • Introduce the double-inversion technique: inserting two inversions that cancel out
  • Ask students: "Why would we want to build a circuit using only one type of gate?"

During the Simulation (15 minutes)

  1. Start with AB + CD in AND-OR form
  2. View the NAND-only equivalent and identify where double inversions were inserted
  3. View the NOR-only equivalent and compare the gate count
  4. Move to a more complex expression and repeat the analysis
  5. Have students attempt the conversion on paper first, then verify
  6. Create a comparison table showing gate counts for each style

After the Simulation (5 minutes)

  • Discuss why CMOS NAND gates are faster and use fewer transistors than NOR gates
  • Explain how EDA tools perform these conversions automatically during synthesis
  • Preview multi-level optimization and how it differs from two-level conversion

References