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ROM Architecture

Description

This simulation shows the internal architecture of a Read-Only Memory (ROM) with a 3-input address decoder and programmable OR array. Set address inputs to see which word line activates and which output bits are produced.

Learning Objectives

Bloom Level: Understand (L2)

  • Understand ROM structure with decoder and OR array
  • Trace address decoding to word line selection
  • See how stored data appears at ROM outputs
  • Recognize ROM as a fixed AND array with programmable OR array

How to Use

  1. Click the address inputs A2, A1, A0 to toggle between 0 and 1
  2. Watch the decoder select the corresponding word line
  3. See which OR-plane connections produce the output bits
  4. Click connections in the OR array to program the ROM contents

References

  • Unit 11: Programmable Logic Devices - ROM Architecture