Setup & Hold Time / Metastability Explorer

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Description

This MicroSim helps students understand three critical concepts in synchronous digital design: setup time, hold time, and metastability. A positive-edge-triggered D flip-flop is shown alongside a timing diagram with CLK, D, and Q waveforms. Students drag a data-transition marker to move the D signal transition left and right relative to the rising clock edge, watching in real time how the flip-flop output changes from a valid capture (green), through a marginal zone (yellow), to a timing violation that produces metastability (red).

The setup time (tsu) is the minimum time the data input must be stable before the clock edge, and the hold time (th) is the minimum time data must remain stable after the clock edge. When either constraint is violated, the flip-flop may enter a metastable state—an indeterminate condition where the output oscillates unpredictably before eventually settling to 0 or 1. Metastability is a fundamental hazard in digital systems and is a key reason why careful timing analysis is essential.

Key Features

  • ● Draggable data-transition marker to explore timing interactively
  • ● Color-coded zones: green (valid), yellow (marginal), red (violation/metastable)
  • ● Shaded setup and hold time windows on the timing diagram
  • ● Animated metastable oscillation on Q when timing is violated
  • ● Adjustable setup and hold time requirements via sliders
  • ● Flip-flop symbol that changes color to indicate current state

Learning Objectives

Bloom Level: Understand (L2)

After using this MicroSim, students will be able to:

  • ✓ Explain the meaning of setup time and hold time constraints for edge-triggered flip-flops
  • ✓ Identify when a data signal violates setup or hold timing constraints
  • ✓ Describe the consequences of setup/hold violations, including metastability
  • ✓ Relate timing margins to reliable flip-flop operation in synchronous designs

How to Use

  1. Observe the timing diagram showing CLK, D, and Q waveforms with the setup and hold windows shaded around the rising clock edge
  2. Drag the orange data-transition marker left or right to move where D changes relative to the clock edge
  3. Watch the status panel change from green (valid capture) to yellow (marginal) to red (metastable) as the data transition enters the forbidden zone
  4. Notice the Q output: it shows a clean 0 or 1 when timing is met, but displays an oscillating "?" when a violation occurs
  5. Adjust the setup time (tsu) and hold time (th) sliders to see how different flip-flop specifications change the size of the forbidden window
  6. Experiment with extreme slider values to understand how tighter timing constraints make violations more likely

References