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VHDL Flip-Flop Patterns

Description

This simulation shows common VHDL coding patterns for D flip-flop variants including basic DFF, DFF with synchronous reset, DFF with asynchronous reset, and DFF with enable. Each variant shows its VHDL code and timing diagram.

Learning Objectives

Bloom Level: Apply (L3)

  • Write VHDL process statements for flip-flop variants
  • Distinguish synchronous vs asynchronous reset patterns
  • Understand clock enable implementation
  • Read timing diagrams for each variant

How to Use

  1. Select a flip-flop variant using the tabs at the top
  2. View the VHDL code showing the process statement
  3. Observe the timing diagram showing CLK, D, RST/EN, and Q signals
  4. Click Clock to advance the timing simulation
  5. Toggle D, RST, and EN inputs to see behavior changes

References

  • Unit 12: VHDL - Sequential Logic Patterns