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VHDL FSM Mapper

Description

This simulation shows the correspondence between VHDL finite state machine code and its state diagram. Click on states or transitions in either view to see the corresponding element highlighted in both representations.

Learning Objectives

Bloom Level: Analyze (L4)

  • Map VHDL FSM code constructs to state diagram elements
  • Identify state type declarations, transition logic, and output logic
  • Trace state transitions between code and diagram
  • Understand the two-process FSM coding pattern

How to Use

  1. Click on a state in the diagram to highlight its code
  2. Click on a transition arrow to see the corresponding WHEN clause
  3. Click on code lines to highlight the diagram element
  4. Use the Step button to simulate FSM operation
  5. Toggle the input to change transition paths

References

  • Unit 12: VHDL - FSM Design and Coding