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VHDL FSM Implementation Walkthrough

Description

This interactive walkthrough bridges state diagrams to VHDL code by implementing a "101" sequence detector as a Moore FSM. Each step builds a VHDL construct: type declaration, state register, next-state logic, and output logic.

Learning Objectives

Bloom Level: Apply (L3)

  • Apply VHDL coding patterns for finite state machines
  • Translate a state diagram into VHDL processes
  • Understand the separation of sequential and combinational logic in FSMs
  • Verify FSM behavior by tracing an input sequence

How to Use

  1. Click Next → to advance through each VHDL coding step
  2. Watch the state diagram translate into VHDL constructs
  3. See the state register, next-state, and output processes build up
  4. Verify by tracing the input sequence 1-0-1 through the FSM
  5. Click ← Previous to review earlier steps
  6. Click Reset to start over

References

  • Unit 12: Introduction to VHDL - FSM Design Patterns