Frequently Asked Questions

This FAQ addresses common questions about the Introduction to Digital System Design course (EE 2301). Questions are organized by category to help you find answers quickly.

Getting Started Questions

What is this course about?

This course provides a comprehensive introduction to the fundamentals of digital system design. You will learn how digital circuits process information using binary number systems and Boolean algebra. The course covers mathematical foundations, analysis techniques, and design methodologies essential for creating digital logic circuits. Topics progress from number representations through Boolean algebra to systematic methods for designing and simplifying combinational logic circuits.

For full details, see the Course Description.

Start with Unit 1 - Number Systems to begin building foundational skills.

Who is this course designed for?

This course is designed for sophomore and junior-level Electrical Engineering students, Computer Engineering students, students pursuing minors in electronics or embedded systems, and anyone seeking foundational knowledge in digital logic design. The material assumes a college-level audience with basic mathematical background.

Begin with Unit 1 - Number Systems to see the starting level of material covered.

What prerequisites do I need before starting?

Before beginning this course, you should have:

Basic algebra and mathematical reasoning skills
Introduction to programming in any language
Familiarity with basic circuit concepts (recommended but not required)

No prior knowledge of digital logic or Boolean algebra is assumed—the course builds these concepts from the ground up.

No prior digital logic knowledge is needed—Unit 1 builds from the ground up.

How is this textbook organized?

The textbook is organized into thirteen units that build progressively:

Unit 1 - Number Systems: Binary, octal, hexadecimal representations and arithmetic
Unit 2 - Boolean Algebra: Logic operations, gates, and algebraic theorems
Unit 3 - Applications of Boolean Algebra: Adders, subtractors, and combinational circuits
Unit 4 - Minterm & Maxterm Expansions: Canonical forms (SOP/POS)
Unit 5 - Karnaugh Maps: Visual simplification method
Unit 6 - Quine-McCluskey Method: Algorithmic minimization
Unit 7 - Multi-Level Gate Circuits: NAND/NOR conversions, bubble pushing, propagation delay
Unit 8 - Combinational Logic Modules: MUX, decoders, encoders, comparators
Unit 9 - Sequential Logic Fundamentals: Latches, flip-flops, timing parameters
Unit 10 - Sequential Circuit Design: Registers, counters, finite state machines
Unit 11 - Programmable Logic Devices: ROM, PLA, PAL, CPLD, FPGA
Unit 12 - Introduction to VHDL: Hardware description language for digital design
Unit 13 - System Integration: Top-down design, datapath-controller, verification

Each unit includes content, worked examples, diagrams, a quiz, practice problems, and a challenge.

What learning resources are available?

The textbook provides multiple learning resources:

410 concepts organized in a learning graph
398 glossary terms with definitions and examples
130 quiz questions (10 per unit) with detailed explanations
106 interactive MicroSims for hands-on practice
95 diagrams illustrating key concepts
4,402 equations in LaTeX format

See the Glossary for term definitions.

Each unit — starting with Unit 1 — includes content, quizzes, problems, a glossary, and references.

How should I use the MicroSims?

MicroSims are interactive simulations built with p5.js that let you explore concepts hands-on. They are particularly valuable for understanding the Quine-McCluskey method in Unit 6. Use them to:

Visualize abstract algorithms step-by-step
Experiment with different inputs to see results
Build intuition before working practice problems

Access all simulations from the MicroSims page.

For example, the Unit 6 - Quine-McCluskey MicroSims let you step through the algorithm interactively.

What is the recommended study approach?

We recommend studying units in order since concepts build on each other. For each unit:

Read the content and study worked examples
Review related glossary terms you don't recognize
Try the MicroSims to reinforce understanding
Take the unit quiz to assess your knowledge
Review any concepts you missed in the quiz

Apply this approach starting with Unit 1 - Number Systems and work through each unit in order.

How do I navigate the textbook?

Use the navigation menu on the left to access units, quizzes, and resources. The search feature (keyboard shortcut: /) helps find specific topics. Each page has a table of contents on the right for section navigation.

Try starting with Unit 1 - Number Systems to explore the layout.

Can I use this textbook offline?

The textbook is designed as an online resource, but you can clone the GitHub repository and build it locally using MkDocs. This allows offline access to all content except external links.

After building locally, verify by opening Unit 1 to confirm all content renders.

How is my learning assessed?

Each unit includes a 10-question multiple-choice quiz aligned with Bloom's Taxonomy cognitive levels. Questions test Remember, Understand, Apply, and Analyze skills. Detailed explanations accompany each answer to support learning.

Try the quiz in Unit 1 to experience the format firsthand.

Core Concept Questions

What is a digital system?

A digital system is an electronic circuit that processes information using discrete signal levels rather than continuous values. Unlike analog systems that work with continuous signals, digital systems represent information using only two distinct states: high voltage (logic 1) and low voltage (logic 0). This binary representation enables superior noise immunity and allows information to be stored and transmitted without degradation.

For more details, see Unit 1 - Number Systems.

Why do computers use binary instead of decimal?

Computers use binary because electronic circuits can reliably distinguish between two voltage states (high and low) but struggle to differentiate many voltage levels accurately. Binary representation offers excellent noise immunity—small voltage fluctuations don't change the logical interpretation. Additionally, binary arithmetic and logic are simpler to implement in hardware than decimal operations.

See Unit 1 - Number Systems for a full treatment of binary representation.

What is positional notation?

Positional notation is a number representation system where the value of each digit depends on both the digit itself and its position. In decimal (base 10), the number 247 means 2×100 + 4×10 + 7×1. The same principle applies to binary (base 2), octal (base 8), and hexadecimal (base 16). Each position represents a power of the base.

See Unit 1 - Number Systems for detailed coverage of positional notation across bases.

What is the difference between signed and unsigned numbers?

Unsigned numbers represent only non-negative values (0 and positive integers). An 8-bit unsigned number ranges from 0 to 255.

Signed numbers can represent both positive and negative values using encoding schemes like two's complement. An 8-bit two's complement number ranges from -128 to +127.

The interpretation depends on context—the same bit pattern can represent different values depending on whether it's treated as signed or unsigned.

See Unit 1 - Number Systems for worked examples of each representation.

What is two's complement and why is it important?

Two's complement is the standard representation for signed integers in modern computers. To find the two's complement of a number: invert all bits and add 1. For example, to represent -5 in 8 bits: start with +5 (00000101), invert to get 11111010, add 1 to get 11111011.

Two's complement is important because it allows addition and subtraction to use the same hardware circuit—subtraction is performed by adding the two's complement of the subtrahend.

See Unit 1 - Number Systems for worked examples.

What is Boolean algebra?

Boolean algebra is a mathematical system for manipulating logical values, developed by George Boole in 1854. Unlike regular algebra that operates on real numbers, Boolean algebra operates exclusively on binary values (0 and 1). This makes it perfectly suited for digital electronics. Boolean algebra provides the theoretical foundation for analyzing and simplifying digital circuits.

Learn more in Unit 2 - Boolean Algebra.

What are the three basic Boolean operations?

The three fundamental Boolean operations are:

AND (·): Returns 1 only when ALL inputs are 1
OR (+): Returns 1 when AT LEAST ONE input is 1
NOT ('): Inverts the input—0 becomes 1, 1 becomes 0

All other Boolean operations (NAND, NOR, XOR, XNOR) can be constructed from these three basic operations.

See Unit 2 - Boolean Algebra for truth tables, gate symbols, and extended operations.

What is DeMorgan's theorem?

DeMorgan's theorem consists of two rules for complementing Boolean expressions:

(A·B)' = A' + B' — The complement of AND equals OR of complements
(A+B)' = A'·B' — The complement of OR equals AND of complements

These theorems are essential for simplifying Boolean expressions and converting between gate types. They extend to any number of variables.

See Unit 2 - Boolean Algebra for proofs and Unit 7 - Multi-Level Gate Circuits for gate conversion applications.

What are universal gates?

Universal gates are logic gates that can implement any Boolean function when used alone. NAND and NOR are both universal gates. Any circuit—including AND, OR, and NOT—can be built using only NAND gates or only NOR gates. This property is valuable in manufacturing because it allows entire circuits to be built with a single gate type.

See Unit 7 - Multi-Level Gate Circuits for NAND-only and NOR-only circuit design.

What is a truth table?

A truth table is a complete listing of all possible input combinations and their corresponding outputs for a logic function. For n inputs, the table has 2^n rows. Truth tables provide an unambiguous specification of circuit behavior and serve as the starting point for deriving Boolean expressions.

See Unit 2 - Boolean Algebra for how truth tables derive Boolean expressions.

What is combinational logic?

Combinational logic circuits produce outputs that depend only on current input values—they have no memory of past inputs. Examples include adders, multiplexers, and decoders. This contrasts with sequential logic, where outputs depend on both current inputs and the circuit's history (state).

See Unit 3 - Applications of Boolean Algebra.

What is the difference between a half adder and full adder?

A half adder adds two single bits, producing a sum and carry output. It cannot handle an incoming carry from a previous stage.

A full adder adds three bits (two operands plus a carry-in), producing a sum and carry-out. Full adders can be cascaded to build multi-bit adders like the ripple carry adder.

See Unit 3 - Applications of Boolean Algebra for complete adder designs with circuit diagrams.

What is a minterm?

A minterm is a product term containing ALL variables of a function, where each variable appears exactly once in either complemented or uncomplemented form. For function F(A,B,C), the minterm m₅ = A·B'·C corresponds to input combination 101 (where A=1, B=0, C=1). A function can be expressed as a sum of its minterms (SOP canonical form).

See Unit 4 - Minterm & Maxterm Expansions.

What is a maxterm?

A maxterm is a sum term containing ALL variables of a function, where each variable appears exactly once. For function F(A,B,C), maxterm M₃ = A + B + C' corresponds to input 011. A function can be expressed as a product of its maxterms (POS canonical form). Note that the variable is complemented from its value in the input combination (opposite of minterms).

See Unit 4 - Minterm & Maxterm Expansions for maxterms, POS canonical forms, and the duality with minterms.

What is the difference between SOP and POS forms?

Sum of Products (SOP): An OR of AND terms, like F = AB + A'C + BC. Each product term can contain any subset of variables.

Product of Sums (POS): An AND of OR terms, like F = (A+B)(A'+C). Each sum term can contain any subset of variables.

Both forms can represent any Boolean function. The choice between them depends on which yields a simpler expression for the specific function.

See Unit 4 for canonical forms and Unit 5 for simplification of both.

What is a Karnaugh map?

A Karnaugh map (K-map) is a graphical tool for simplifying Boolean expressions. It arranges minterms in a 2D grid where adjacent cells differ by exactly one variable. This allows visual identification of terms that can be combined, eliminating variables to produce simpler expressions. K-maps are practical for functions with up to 5-6 variables.

Learn the technique in Unit 5 - Karnaugh Maps.

What is a prime implicant?

A prime implicant is a product term that covers one or more minterms of a function and cannot be combined with another term to form a larger implicant. In a K-map, a prime implicant corresponds to a group that cannot be made larger without including cells where the function is 0. Every minimal expression is composed of prime implicants.

See Unit 5 - Karnaugh Maps for visual identification and Unit 6 - Quine-McCluskey for the tabular approach.

What is an essential prime implicant?

An essential prime implicant is the ONLY prime implicant covering at least one minterm. Essential prime implicants must appear in any minimal solution. In a K-map, if a 1-cell is covered by only one maximal group, that group represents an essential prime implicant.

See Unit 5 and Unit 6 for identification techniques.

What is the Quine-McCluskey method?

The Quine-McCluskey (QM) method is a systematic tabular algorithm for finding the minimal sum-of-products expression. Unlike K-maps which rely on visual pattern recognition, QM follows a deterministic procedure that can be automated by computer. It works for any number of variables and guarantees finding all prime implicants.

See Unit 6 - Quine-McCluskey Method.

What are don't care conditions?

Don't care conditions are input combinations for which the output value is unspecified—either because those inputs never occur or because the output doesn't matter. In optimization, don't cares can be treated as 1 or 0, whichever produces a simpler expression. For example, in a BCD decoder, inputs 1010-1111 are don't cares because they're invalid BCD values.

See Unit 5 - Karnaugh Maps for handling don't cares in K-map grouping.

Technical Detail Questions

What is the difference between a bit, nibble, byte, and word?

Bit: Single binary digit (0 or 1)
Nibble: 4 bits—represents one hexadecimal digit
Byte: 8 bits—common unit for data storage
Word: Processor-dependent size (typically 16, 32, or 64 bits)

These terms describe data sizes at different granularities in computer systems.

See Unit 1 - Number Systems for how these data sizes appear in binary and hexadecimal contexts.

How do I convert between number bases?

Decimal to binary: Repeatedly divide by 2, collect remainders in reverse order.

Binary to decimal: Sum the weighted values (each bit times 2^position).

Binary to hexadecimal: Group bits into nibbles (4 bits), convert each group.

Hexadecimal to binary: Expand each hex digit to 4 bits.

See the Glossary for conversion examples.

Step-by-step conversion methods are covered in Unit 1 - Number Systems.

What is overflow and how do I detect it?

Overflow occurs when an arithmetic result exceeds the range representable in the available bits. In two's complement:

Overflow occurs if two positive numbers produce a negative result
Overflow occurs if two negative numbers produce a positive result
Overflow CANNOT occur when adding numbers of opposite signs

Detection: Compare the carry into the sign bit with the carry out. If they differ, overflow occurred.

See Unit 1 - Number Systems for overflow detection in two's complement arithmetic.

What are the Boolean algebra laws I need to know?

Essential laws include:

Identity: A+0=A, A·1=A
Null: A+1=1, A·0=0
Complement: A+A'=1, A·A'=0
Commutative: A+B=B+A, A·B=B·A
Associative: (A+B)+C=A+(B+C)
Distributive: A·(B+C)=A·B+A·C
Absorption: A+A·B=A
DeMorgan's: (A·B)'=A'+B', (A+B)'=A'·B'

See Unit 2 - Boolean Algebra for proofs and applications of each law.

What is operator precedence in Boolean algebra?

The standard precedence (highest to lowest) is:

NOT (complement) — evaluated first
AND — evaluated second
OR — evaluated last

So A + B·C means A + (B·C), not (A+B)·C. Use parentheses when needed to override precedence.

See Unit 2 - Boolean Algebra for how precedence applies in simplification.

What is Gray code and why is it used?

Gray code is a binary encoding where adjacent values differ by exactly one bit. The sequence is: 00, 01, 11, 10 (for 2 bits). Gray code is used in K-maps to ensure adjacent cells differ by one variable. It's also used in rotary encoders and other applications where minimizing bit transitions reduces errors.

See Unit 5 - Karnaugh Maps for how Gray code ordering enables K-map adjacency.

What is the difference between logical and physical adjacency in K-maps?

Logical adjacency: Two cells are logically adjacent if their minterms differ by exactly one variable.

Physical adjacency: Cells that are next to each other on the K-map grid.

Due to Gray code ordering and wraparound, physically distant cells (like opposite edges or corners) can be logically adjacent. Always consider wraparound when grouping.

See Unit 5 - Karnaugh Maps for complete coverage of wraparound adjacency.

What group sizes are valid in K-maps?

Valid group sizes must be powers of 2: 1, 2, 4, 8, 16, etc. Groups must also be rectangular. Valid configurations include:

1×1, 1×2, 2×1, 1×4, 4×1, 2×2, 2×4, 4×2, 4×4

Groups of 3, 5, 6, or other non-power-of-2 sizes are invalid.

See Unit 5 - Karnaugh Maps for grouping rules and variable elimination.

What is Petrick's method?

Petrick's method is an algebraic technique for finding minimum covers when a prime implicant chart has no essential prime implicants (cyclic chart). It creates a Boolean expression representing all valid covers, then finds the minimum-cost solutions by expanding and simplifying this expression.

See Unit 6 - Quine-McCluskey Method for a worked example with cyclic charts.

How does the Quine-McCluskey algorithm work?

The QM algorithm has two main phases:

Find all prime implicants: Group minterms by the number of 1-bits. Combine terms that differ by one bit, marking combined terms. Repeat until no more combinations. Unchecked terms are prime implicants.
Find minimum cover: Build a chart showing which minterms each PI covers. Select essential PIs (those uniquely covering a minterm). For remaining minterms, select additional PIs to achieve minimum cost.

See Unit 6 - Quine-McCluskey Method for a complete step-by-step walkthrough.

What is the computational complexity of Quine-McCluskey?

The QM algorithm has exponential complexity. For n variables, the maximum number of prime implicants is approximately 3^n/n. This makes QM impractical for functions with many variables (beyond ~15-20). For small functions, QM guarantees optimal results; for larger functions, heuristic methods are used.

See Unit 6 - Quine-McCluskey Method for algorithm complexity and practical limits.

Common Challenge Questions

Why am I getting wrong answers in two's complement arithmetic?

Common mistakes include:

Not handling overflow: Check if the result exceeds the representable range
Incorrect sign extension: When working with different bit widths, extend the sign bit
Confusing signed and unsigned: Know which interpretation applies
Wrong conversion: To negate, invert ALL bits then add 1

Work through the conversion step-by-step and verify with decimal equivalents.

Review Unit 1 - Number Systems for worked examples of two's complement conversion and overflow detection.

How do I simplify Boolean expressions algebraically?

Apply these techniques systematically:

Apply DeMorgan's theorem to eliminate long complements
Factor common terms using the distributive law
Look for absorption (A + AB = A)
Apply the complement law (A + A' = 1, A·A' = 0)
Use the consensus theorem when applicable

Practice with simple expressions before tackling complex ones.

See Unit 2 - Boolean Algebra for algebraic laws and worked simplification examples.

Why won't my K-map groups simplify further?

Check these common issues:

Invalid group size: Must be 1, 2, 4, 8, or 16 cells
Non-rectangular shape: Groups must be rectangles
Missed wraparound: Edges and corners can connect
Not maximizing groups: Each group should be as large as possible
Uncovered 1s: Every 1-cell must belong to at least one group

See Unit 5 - Karnaugh Maps for systematic grouping rules and common mistakes.

How do I handle don't cares in K-maps?

Include don't care cells (marked X or d) in groups ONLY when it makes the group larger. You're not required to cover don't cares, but you can treat them as 1s if it helps simplification. Never group don't cares alone—only include them to expand groups of actual 1s.

See Unit 5 - Karnaugh Maps for worked examples with don't care cells.

When should I use K-maps versus Quine-McCluskey?

Use K-maps when: - Function has 2-5 variables - You want quick visual identification of groups - Manual calculation is acceptable

Use Quine-McCluskey when: - Function has 6+ variables - You need guaranteed optimal solution - Algorithm will be computerized - Multiple output functions share terms

Review Unit 5 and Unit 6 to understand where each method excels.

Why do I get different minimal expressions from K-maps?

Multiple minimal expressions can exist for the same function. This happens when different grouping choices yield expressions with equal cost (same literal count). All valid minimal expressions are correct—they implement the same function. The QM method can find all minimum covers.

See Unit 5 - Karnaugh Maps for examples of multiple valid groupings.

How do I convert between SOP and POS forms?

SOP to POS: 1. Create truth table from SOP 2. Identify rows where function = 0 3. Write maxterms for those rows 4. Product the maxterms

Alternative: Apply DeMorgan's theorem to the complement.

POS to SOP: Similar process using rows where function = 1.

See Unit 4 - Minterm & Maxterm Expansions for the underlying minterm/maxterm duality.

What if my K-map has all 1s or all 0s?

All 1s: The function equals 1 (constant). Expression: F = 1
All 0s: The function equals 0 (constant). Expression: F = 0
Half 1s in a pattern: Look for single-variable expressions like F = A or F = A'

See Unit 5 - Karnaugh Maps for degenerate cases and constant functions.

How do I identify prime implicants in the QM method?

A term is a prime implicant if it: 1. Was never combined with another term (no check mark), OR 2. Cannot be combined further in subsequent iterations

After completing all combination iterations, collect all unchecked terms from all columns. These are your prime implicants.

See Unit 6 - Quine-McCluskey Method for a complete worked example tracing prime implicant identification.

Best Practice Questions

How do I approach a digital logic design problem?

Follow this systematic approach:

Understand requirements: Identify inputs, outputs, and behavior
Create truth table: List all input combinations and outputs
Write canonical form: Express as sum of minterms or product of maxterms
Simplify: Use K-maps or QM method
Draw circuit: Implement with logic gates
Verify: Check against original truth table

This process is demonstrated end-to-end in Unit 3 - Applications of Boolean Algebra.

What is the most efficient way to simplify expressions?

For efficiency:

2-4 variables: Use K-maps—fastest manual method
5-6 variables: K-maps still work but require care with 5-variable maps
7+ variables: Use Quine-McCluskey with computer assistance
Multiple outputs: Consider shared terms across functions

Always verify your simplified expression against the original truth table.

See Unit 5 for K-map techniques and Unit 6 for algorithmic minimization.

When should I use NAND-only or NOR-only implementations?

Use universal gate implementations when:

Manufacturing requires single gate type
Cost optimization favors one gate type
Design rules specify NAND or NOR (common in CMOS)

Convert from SOP (for NAND) or POS (for NOR) using DeMorgan's theorem.

See Unit 7 - Multi-Level Gate Circuits for systematic NAND and NOR conversion procedures.

How do I minimize literal count effectively?

Strategies for literal minimization:

Maximize group sizes: Larger groups eliminate more variables
Exploit don't cares: Include them to enlarge groups
Consider POS alternative: Sometimes POS has fewer literals than SOP
Factor common terms: A(B+C) has fewer literals than AB+AC

See Unit 5 and Unit 7 for literal and gate count minimization techniques.

What makes a good circuit design?

Good designs balance:

Correctness: Matches specification (truth table)
Minimal gates: Reduces cost and power
Minimal literals: Reduces gate inputs
Speed: Consider propagation delay paths
Testability: Can faults be detected?

See Unit 7 for gate optimization and Unit 13 for verification and testability.

How should I organize my K-map work?

Best practices:

Label rows and columns clearly with Gray code order
Fill in all cells before grouping
Use different colors or patterns for different groups
Write the product term next to each group
Clearly mark overlapping cells
Check that all 1s are covered

See Unit 5 - Karnaugh Maps for worked examples demonstrating these practices.

When are multiple solutions acceptable?

Multiple minimal solutions are acceptable when:

They have the same literal count (same cost)
Either implements the correct function
Other constraints (like sharing terms) don't apply

Document your solution clearly, noting that alternatives exist.

See Unit 5 and Unit 6 for examples where multiple minimum covers exist.

Advanced Topics Questions

How does multi-output minimization work?

Multi-output minimization finds shared product terms across several functions to reduce total gates. For example, if F₁ and F₂ both need term AB, implementing AB once and sharing it reduces gate count. The Quine-McCluskey method can be extended to find shared prime implicants.

See Unit 6 - Quine-McCluskey Method for multi-output extensions of the QM algorithm.

What are the limits of K-map and QM methods?

K-map limits: - Impractical beyond 5-6 variables - Manual process prone to human error - Doesn't scale to industrial problems

QM limits: - Exponential complexity (3^n/n worst case) - Impractical for 20+ variables - Memory intensive for large problems

Modern tools use heuristics like ESPRESSO for industrial-scale problems.

See Unit 5 and Unit 6 for the practical boundaries of each method.

How do hazards affect combinational circuits?

Hazards are momentary incorrect outputs during signal transitions. Static hazards produce a brief glitch (0 or 1) when output should remain constant. They occur when two overlapping groups don't share a cell. Hazards can be eliminated by adding redundant groups to cover transition paths.

See Unit 7 - Multi-Level Gate Circuits for hazard analysis and the redundant group elimination technique.

What is the relationship between Boolean algebra and set theory?

Boolean algebra and set theory share algebraic structure:

AND corresponds to intersection
OR corresponds to union
NOT corresponds to complement
1 corresponds to universal set
0 corresponds to empty set

All Boolean theorems have set theory equivalents.

See Unit 2 - Boolean Algebra for the axiomatic foundations of Boolean algebra.

How do sequential circuits differ from combinational circuits?

Combinational: Output depends only on current inputs. No memory. Examples: adders, decoders.

Sequential: Output depends on current inputs AND past history (state). Has memory elements (flip-flops). Examples: counters, registers, finite state machines.

Sequential circuits are covered in detail in Unit 9 and Unit 10.

What is a flip-flop and how does it differ from a latch?

A latch is level-sensitive: its output follows the input whenever the enable signal is active (transparent mode). A flip-flop is edge-triggered: it samples the input only at the instant of a clock edge (rising or falling) and ignores input changes at all other times. Flip-flops provide predictable, single-sample-per-cycle behavior essential for synchronous design.

D latch: Q follows D while Enable = 1; holds when Enable = 0
D flip-flop: Q captures D only at the rising clock edge

See Unit 9 for complete coverage.

What is a finite state machine (FSM)?

A finite state machine is a sequential circuit with a finite number of states, transitions between states driven by inputs, and outputs determined by the current state (Moore) or state and inputs (Mealy). FSMs are used to model control logic for systems like traffic lights, vending machines, and protocol handlers.

Moore machine: Output depends only on the current state
Mealy machine: Output depends on both the current state and current input

See Unit 10 for FSM design methodology.

What is the difference between a Moore and Mealy machine?

Both are finite state machine models:

Moore: Outputs are associated with states. Output changes only at clock edges when the state transitions. Generally requires more states but produces glitch-free outputs.
Mealy: Outputs are associated with transitions. Output can change asynchronously when inputs change during a clock cycle. Uses fewer states but outputs may glitch.

For the same behavior, a Mealy machine typically produces output one clock cycle earlier than a Moore machine. See Unit 10.

What is an FPGA and why is it important?

A Field-Programmable Gate Array (FPGA) is an integrated circuit containing an array of configurable logic blocks (CLBs), programmable interconnects, and I/O blocks that can be programmed by the end user to implement virtually any digital circuit. FPGAs are important because they:

Allow rapid prototyping without custom chip fabrication
Can be reprogrammed for different designs
Bridge the gap between software simulation and ASIC production
Are used in telecommunications, aerospace, automotive, and data centers

See Unit 11 for PLD architectures.

What is VHDL and how is it used?

VHDL (VHSIC Hardware Description Language) is an IEEE-standard language used to describe, simulate, and synthesize digital circuits. A VHDL design consists of:

Entity declaration: Defines the external interface (ports and their types)
Architecture body: Describes the internal implementation (behavioral, dataflow, or structural)

VHDL supports three modeling styles: behavioral (algorithmic), dataflow (concurrent signal assignments), and structural (component instantiation). See Unit 12.

What is Shannon expansion and when is it used?

Shannon expansion (also called the expansion theorem) expresses a Boolean function in terms of its cofactors with respect to a variable:

F = x · F_x + x' · F_x'

where F_x is the cofactor obtained by setting x = 1. This technique is used for:

Implementing functions with multiplexers (MUX-based design)
Decomposing complex functions into simpler subfunctions
Binary decision diagram (BDD) construction

See Unit 4 for details.

What is an entered variable K-map?

An entered variable K-map reduces the map size by entering variables or expressions into cells instead of just 0s and 1s. A function of n variables can be represented on an (n-1)-variable map by entering the remaining variable in the cells.

For example, a 5-variable function can be plotted on a 4-variable K-map with the fifth variable entered in cells. This technique is particularly useful for functions with more than 4 variables where standard K-maps become unwieldy.

See Unit 5.

How does a parity checker work?

A parity checker verifies whether received data has the correct parity:

Even parity: Total number of 1-bits (data + parity bit) should be even
Odd parity: Total number of 1-bits should be odd

The checker XORs all received bits (including the parity bit). If the result is 0 for even parity (or 1 for odd parity), no error is detected. A non-zero result indicates a single-bit error occurred during transmission.

See Unit 3.

What is the consensus theorem used for?

The consensus theorem states that AB + A'C + BC = AB + A'C, meaning the term BC is redundant. It is used to:

Simplify Boolean expressions by identifying and removing consensus (redundant) terms
Verify K-map results algebraically
Recognize optimization opportunities in multi-level circuits

The dual form is: (A+B)(A'+C)(B+C) = (A+B)(A'+C). See Unit 2.

What are the IEEE standard gate symbols?

IEEE standard symbols (IEEE Std 91) use rectangular blocks with qualifying symbols inside to represent logic functions, as an alternative to the distinctive-shape symbols most students learn first:

AND: Rectangle with & symbol
OR: Rectangle with ≥1 symbol
NOT: Rectangle with 1 and a triangle/bubble on output
XOR: Rectangle with =1 symbol

Both symbol sets are used in industry. See Unit 2.

What is a buffer gate used for?

A buffer gate produces an output identical to its input (Y = A). While it performs no logical transformation, buffers serve important practical purposes:

Signal amplification: Restoring degraded voltage levels
Fan-out management: Driving multiple gate inputs from a single source
Propagation delay insertion: Adding controlled delay to timing-critical paths
Isolation: Preventing loading effects between circuit stages

See Unit 2.

How do I handle fractional numbers in binary?

Fractional binary numbers use a radix point (binary point) to separate integer and fractional parts. Each position to the right of the radix point represents a negative power of 2:

Position -1: 2^(-1) = 0.5
Position -2: 2^(-2) = 0.25
Position -3: 2^(-3) = 0.125

Decimal to binary fraction: Multiply by 2 repeatedly, recording integer parts. For example, 0.625 → 0.625×2 = 1.25 (1), 0.25×2 = 0.5 (0), 0.5×2 = 1.0 (1), giving 0.101 in binary.

Note: Some decimal fractions (like 0.1) produce infinite repeating binary representations. See Unit 1.

What is static timing analysis?

Static timing analysis (STA) verifies circuit timing by computing worst-case signal propagation delays through all paths without requiring simulation. It checks that:

Setup time: Data arrives at each flip-flop's input early enough before the clock edge
Hold time: Data remains stable long enough after the clock edge

The maximum clock frequency is determined by: f_max = 1 / (t_cq + t_logic_max + t_setup)

STA is faster and more comprehensive than timing simulation because it analyzes all paths, not just those exercised by test vectors. See Unit 13.

What are the industry applications of these concepts?

Digital system design concepts apply to:

Processor design: ALUs, control logic
Memory systems: Address decoders, error correction
Communication: Protocol logic, encoding/decoding
Embedded systems: Sensor interfaces, control logic
FPGA programming: Hardware description languages use Boolean concepts

See Unit 11, Unit 12, and Unit 13 for how these concepts are applied in real industry workflows.

Resources

Course Description - Full course details and learning outcomes
Glossary - 398 term definitions with examples
MicroSims - Interactive simulations
Book Metrics - Content statistics