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Concept List

This document contains 410 concepts for the Introduction to Digital System Design course (EE 2301).

Unit 1: Number Systems (1-40)

  1. Digital Systems
  2. Analog vs Digital Signals
  3. Binary Number System
  4. Decimal Number System
  5. Octal Number System
  6. Hexadecimal Number System
  7. Positional Notation
  8. Base of Number System
  9. Radix Point
  10. Bit
  11. Nibble
  12. Byte
  13. Word
  14. Most Significant Bit
  15. Least Significant Bit
  16. Binary to Decimal Conversion
  17. Decimal to Binary Conversion
  18. Octal to Decimal Conversion
  19. Decimal to Octal Conversion
  20. Hexadecimal to Decimal
  21. Decimal to Hexadecimal
  22. Binary to Octal Conversion
  23. Octal to Binary Conversion
  24. Binary to Hexadecimal
  25. Hexadecimal to Binary
  26. Binary Addition
  27. Binary Subtraction
  28. Binary Multiplication
  29. Binary Division
  30. Signed Numbers
  31. Unsigned Numbers
  32. Sign Magnitude
  33. Ones Complement
  34. Twos Complement
  35. Sign Extension
  36. Twos Complement Addition
  37. Twos Complement Subtraction
  38. Overflow Detection
  39. Underflow
  40. Range of Signed Numbers

Unit 2: Boolean Algebra (41-90)

  1. Boolean Algebra
  2. Boolean Variable
  3. Boolean Constant
  4. Logic Levels
  5. High and Low States
  6. Truth Value
  7. AND Operation
  8. OR Operation
  9. NOT Operation
  10. Complement
  11. Logic Gates
  12. AND Gate
  13. OR Gate
  14. NOT Gate
  15. Inverter
  16. NAND Gate
  17. NOR Gate
  18. XOR Gate
  19. XNOR Gate
  20. Buffer Gate
  21. Universal Gates
  22. Gate Symbols
  23. IEEE Gate Symbols
  24. Truth Table
  25. Boolean Expression
  26. Logic Function
  27. Identity Law
  28. Null Law
  29. Idempotent Law
  30. Involution Law
  31. Complement Law
  32. Commutative Law
  33. Associative Law
  34. Distributive Law
  35. Absorption Law
  36. Consensus Theorem
  37. DeMorgans First Theorem
  38. DeMorgans Second Theorem
  39. Duality Principle
  40. Algebraic Simplification
  41. Literal
  42. Product Term
  43. Sum Term
  44. Sum of Products
  45. Product of Sums
  46. Precedence of Operators
  47. Parentheses in Boolean
  48. Multiple Input Gates
  49. Cascading Gates
  50. Fan-In and Fan-Out

Unit 3: Applications of Boolean Algebra (91-125)

  1. Combinational Logic
  2. Sequential Logic
  3. Logic Circuit
  4. Circuit Analysis
  5. Circuit Synthesis
  6. Specification to Circuit
  7. Word Problems to Boolean
  8. Switching Functions
  9. Binary Decision
  10. Enable Signal
  11. Control Signal
  12. Half Adder
  13. Full Adder
  14. Carry Bit
  15. Sum Bit
  16. Ripple Carry Adder
  17. Half Subtractor
  18. Full Subtractor
  19. Borrow Bit
  20. Difference Bit
  21. Adder Subtractor Circuit
  22. Comparator Circuit
  23. Magnitude Comparator
  24. Parity Generator
  25. Parity Checker
  26. Even Parity
  27. Odd Parity
  28. Code Converter
  29. BCD Code
  30. Gray Code
  31. BCD to Binary Converter
  32. Binary to Gray Converter
  33. Seven Segment Display
  34. Seven Segment Decoder
  35. Incompletely Specified Func

Unit 4: Minterm and Maxterm Expansions (126-160)

  1. Canonical Form
  2. Standard Form
  3. Minterm
  4. Maxterm
  5. Minterm Expansion
  6. Maxterm Expansion
  7. Minterm Designation
  8. Maxterm Designation
  9. Sum of Minterms
  10. Product of Maxterms
  11. Minterm to Maxterm
  12. Maxterm to Minterm
  13. Canonical SOP Form
  14. Canonical POS Form
  15. Minterm List Notation
  16. Maxterm List Notation
  17. Sigma Notation
  18. Pi Notation
  19. Complement of Function
  20. Function from Truth Table
  21. Minterm from Truth Table
  22. Maxterm from Truth Table
  23. Dont Care Condition
  24. Incompletely Specified
  25. Dont Care in SOP
  26. Dont Care in POS
  27. Converting SOP to POS
  28. Converting POS to SOP
  29. Expansion Theorem
  30. Shannon Expansion
  31. Cofactor
  32. On-Set of Function
  33. Off-Set of Function
  34. DC-Set of Function
  35. Literal Count

Unit 5: Karnaugh Maps (161-200)

  1. Karnaugh Map
  2. K-Map Structure
  3. K-Map Cell
  4. K-Map Variables
  5. Two Variable K-Map
  6. Three Variable K-Map
  7. Four Variable K-Map
  8. Five Variable K-Map
  9. K-Map Gray Code Order
  10. K-Map Adjacency
  11. Logical Adjacency
  12. Physical Adjacency
  13. K-Map Grouping
  14. Group of Ones
  15. Group of Zeros
  16. Valid Group Sizes
  17. Rectangular Groups
  18. Wrapping in K-Maps
  19. Corner Grouping
  20. Implicant
  21. Prime Implicant
  22. Essential Prime Implicant
  23. Redundant Prime Implicant
  24. K-Map SOP Simplification
  25. K-Map POS Simplification
  26. Minimal SOP Expression
  27. Minimal POS Expression
  28. K-Map with Dont Cares
  29. Using Dont Cares
  30. Overlapping Groups
  31. Covering All Ones
  32. Covering All Zeros
  33. Multiple Solutions
  34. Cost of Expression
  35. Gate Count Minimization
  36. Literal Minimization
  37. K-Map Limitations
  38. Five Variable Technique
  39. Entered Variable K-Map
  40. K-Map vs Algebraic Method

Unit 6: Quine-McCluskey Method (201-225)

  1. Quine-McCluskey Algorithm
  2. Tabular Minimization Method
  3. Implicant Table Construction
  4. Binary Representation of Minterms
  5. Grouping by Number of Ones
  6. Adjacency Criterion in QM
  7. Combining Adjacent Minterms
  8. Dash Notation for Combined Terms
  9. Iterative Combination Process
  10. Unchecked Terms as Prime Implicants
  11. Prime Implicant Chart Construction
  12. Essential Prime Implicants Selection
  13. Row Dominance
  14. Column Dominance
  15. Cyclic Prime Implicant Charts
  16. Petrick's Method
  17. Minimal Cover Selection
  18. QM Method with Don't Cares
  19. Computational Complexity of QM
  20. QM versus K-map Comparison
  21. Multi-Output Function Minimization
  22. Computer Implementation of QM
  23. Literal Count Optimization
  24. Gate Count Optimization
  25. Systematic Approach Advantages

Unit 7: Multi-Level Gate Circuits (226-250)

  1. Two-Level vs Multi-Level Circuits
  2. Two-Level Circuit Definition
  3. Multi-Level Circuit Definition
  4. NAND-NAND Realization
  5. NOR-NOR Realization
  6. NAND-NOR Mixed Networks
  7. NOR-NAND Mixed Networks
  8. Bubble Pushing Technique
  9. Gate-Level Transformation
  10. AOI Gate
  11. OAI Gate
  12. AOI-OAI Circuit Forms
  13. Propagation Delay
  14. Gate Delay Model
  15. Critical Path Analysis
  16. Circuit Delay Optimization
  17. Fan-In Constraints
  18. Multi-Level Fan-In Reduction
  19. Factoring Boolean Expressions
  20. Multi-Level Synthesis from SOP
  21. Multi-Level Synthesis from POS
  22. Algebraic Factoring
  23. Common Sub-expression Elimination
  24. Level Reduction Techniques
  25. Multi-Level Cost Analysis

Unit 8: Combinational Logic Modules (251-275)

  1. Multiplexer
  2. 2-to-1 Multiplexer
  3. 4-to-1 Multiplexer
  4. 8-to-1 Multiplexer
  5. MUX Select Lines
  6. MUX Data Lines
  7. MUX Boolean Expression
  8. MUX-Based Function Implementation
  9. Shannon Expansion for MUX
  10. MUX Tree Implementation
  11. Decoder
  12. 2-to-4 Decoder
  13. 3-to-8 Decoder
  14. Decoder with Enable
  15. Decoder Expansion
  16. Decoder-Based Function Implementation
  17. Encoder
  18. Priority Encoder
  19. Priority Encoder Valid Output
  20. Demultiplexer
  21. Magnitude Comparator Module
  22. Cascading Comparators
  23. Tri-State Buffer
  24. Bus Architecture
  25. Cascading Combinational Modules

Unit 9: Sequential Logic Fundamentals (276-305)

  1. Sequential vs Combinational Logic
  2. Memory Element
  3. Feedback Loop
  4. SR Latch (NOR)
  5. SR Latch (NAND)
  6. SR Latch Invalid State
  7. Gated SR Latch
  8. D Latch
  9. Latch Transparency
  10. Clock Signal
  11. Clock Edge
  12. Edge Triggering
  13. Positive Edge Trigger
  14. Negative Edge Trigger
  15. D Flip-Flop
  16. JK Flip-Flop
  17. T Flip-Flop
  18. Master-Slave Flip-Flop
  19. Setup Time
  20. Hold Time
  21. Clock-to-Q Delay
  22. Metastability
  23. Synchronous Logic
  24. Asynchronous Logic
  25. Timing Diagram
  26. Characteristic Table
  27. Excitation Table
  28. State
  29. Next State
  30. State Transition

Unit 10: Sequential Circuit Design (306-335)

  1. Register
  2. Parallel Load Register
  3. Shift Register
  4. SISO Shift Register
  5. SIPO Shift Register
  6. PISO Shift Register
  7. PIPO Shift Register
  8. Binary Up Counter
  9. Binary Down Counter
  10. Up-Down Counter
  11. Modulo-N Counter
  12. Ring Counter
  13. Johnson Counter
  14. Finite State Machine
  15. State Diagram
  16. State Table
  17. Moore Machine
  18. Mealy Machine
  19. State Assignment
  20. Binary State Encoding
  21. One-Hot State Encoding
  22. Gray Code State Encoding
  23. State Minimization
  24. Next-State Logic
  25. Output Logic
  26. FSM Design Procedure
  27. Timing Analysis for Sequential Circuits
  28. Counter Design Using FSM
  29. Shift Register Applications
  30. Sequential Circuit Synthesis

Unit 11: Programmable Logic Devices (336-365)

  1. Programmable Logic Overview
  2. Fuse Technology
  3. Antifuse Technology
  4. SRAM-Based Programming
  5. ROM
  6. PROM
  7. EPROM
  8. EEPROM
  9. PLA
  10. PAL
  11. PLD Selection Criteria
  12. CPLD
  13. Function Block
  14. Interconnect Matrix
  15. FPGA
  16. Configurable Logic Block
  17. Lookup Table
  18. I/O Block
  19. Routing Resources
  20. FPGA Design Flow
  21. Bitstream
  22. Device Programming
  23. In-System Programming
  24. FPGA vs CPLD Comparison
  25. CLB Interconnect
  26. Logic Capacity Metrics
  27. FPGA Timing Analysis
  28. Partial Reconfiguration
  29. Hard vs Soft IP Cores
  30. PLD Design Entry Methods

Unit 12: Introduction to VHDL (366-395)

  1. Hardware Description Language
  2. VHDL History and IEEE 1076
  3. VHDL Design Entity
  4. Entity Declaration
  5. Port Declaration
  6. Port Modes
  7. Architecture Body
  8. Signal Declaration
  9. Concurrent Signal Assignment
  10. Selected Signal Assignment
  11. Conditional Signal Assignment
  12. Dataflow Modeling Style
  13. Process Statement
  14. Sequential Statements
  15. If-Then-Else Statement
  16. Case Statement
  17. Variables vs Signals
  18. Behavioral Modeling Style
  19. Component Declaration
  20. Component Instantiation
  21. Port Map
  22. Generic Map
  23. Structural Modeling Style
  24. std_logic Type
  25. std_logic_vector
  26. VHDL Operators
  27. Type Conversion
  28. Testbench
  29. Assert and Report
  30. VHDL FSM Implementation

Unit 13: System Integration (396-410)

  1. Top-Down Design Methodology
  2. Hierarchical Decomposition
  3. Datapath Design
  4. Controller Design
  5. Datapath-Controller Partitioning
  6. Control Signals
  7. Status Signals
  8. ASM Chart
  9. Timing Budget
  10. Critical Path in System
  11. Pipelining Concept
  12. System Verification
  13. Design for Testability
  14. UART Protocol Basics
  15. System-Level Debugging